LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

8516 DATA SHEET

2

REVISION B 6/11/15

Number

Name

Type

Description

1, 6, 12,

25, 31, 36

V

DD

Power

Positive supply pins.

2, 3

nQ5, Q5

Output

Differential output pair. LVDS interface levels.

4, 5

nQ4, Q4

Output

Differential output pair. LVDS interface levels.

7, 17, 20,

30, 41, 44

GND

Power

Power supply ground.

8, 9

nQ3, Q3

Output

Differential output pair. LVDS interface levels.

10, 11

nQ2, Q2

Output

Differential output pair. LVDS interface levels.

13, 14

nQ1, Q1

Output

Differential output pair. LVDS interface levels.

15, 16

nQ0, Q0

Output

Differential output pair. LVDS interface levels.

18

nCLK

Input

Pullup

Inverting differential clock input.

19

CLK

Input

Pulldown

Non-inverting differential clock input.

21, 22

Q15, nQ15

Output

Differential output pair. LVDS interface levels.

23, 24

Q14, nQ14

Output

Differential output pair. LVDS interface levels.

26, 27

Q13, nQ13

Output

Differential output pair. LVDS interface levels.

28, 29

Q12, nQ12

Output

Differential output pair. LVDS interface levels.

32, 33

Q11, nQ11

Output

Differential output pair. LVDS interface levels.

34, 35

Q10, nQ10

Output

Differential output pair. LVDS interface levels.

37, 38

Q9, nQ9

Output

Differential output pair. LVDS interface levels.

39, 40

Q8, nQ8

Output

Differential output pair. LVDS interface levels.

42, 43

OE2, OE1

Input

Pullup

Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15; OE1

controls outputs Q0, nQ0 thru Q7, nQ7.

LVCMOS/LVTTL interface levels.

45, 46

nQ7, Q7

Output

Differential output pair. LVDS interface levels.

47, 48

nQ6, Q6

Output

Differential output pair. LVDS interface levels.