LPC83X datasheet(12/78 Pages) NXP

12 / 78 page

LPC83x

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Product data sheet

Rev. 1.2 — 4 April 2018

12 of 78

NXP Semiconductors

LPC83x

32-bit ARM Cortex-M0+ microcontroller

8. Functional description

8.1 ARM Cortex-M0+ core

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a

two-stage pipeline. The core revision is r0p1.

Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two

watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast

GPIO access.

The core includes a single-cycle multiplier and a system tick timer.

8.2 On-chip flash program memory

The LPC83x contain up to 32 KB of on-chip flash program memory. The flash memory

supports a 64 Byte page size with page write and erase.

8.3 On-chip SRAM

The LPC83x contain a total of 4 KB on-chip static RAM data memory.

8.4 On-chip ROM

The on-chip ROM contains the bootloader and the following Application Programming

Interfaces (APIs):

• In-System Programming (ISP) and In-Application Programming (IAP) support for flash

including IAP erase page command.

8.5 Memory map

The LPC83x incorporates several distinct memory regions. Figure 6 shows the overall

map of the entire address space from the user program viewpoint following reset. The

interrupt vector area supports address remapping.

The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,

the system tick timer (SysTick), and the reduced power modes.

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