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Frequency Hold-Over Mode

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

Table 2. LVCMOS Phase Shift Options

Phase

P-Divider

180

°Phase-Shift

P16-Div - Function

0

°

Any P-Divider

No

div-by-16

90

°

P16-Div

No

div-by-4 or div-by-8

180

°

Any P-Divider

Yes

div-by-16

270

°

P16-Div

Yes

div-by-4 or div-by-8

If the P16-Div is selected by the FB_MUX and div-by-4 or div-by-8 is active, the 90 degree phase shifted clock

will be synchronized to PRI_REF or SEC_REF. This means all outputs Yxx, which are switched to div-by-4 or

div-by-8, are in phase to PRI_REF or SEC_REF. All other outputs are 90 degree phase shifted with leading

phase.

The HOLD function is a useful feature which helps the designer to improve the system reliability. The HOLD

function holds the output frequency in case the input reference clock fails or is disrupted. During HOLD, the

charge pump is switched off (3-state) freezing the last valid output frequency. The hold function will be released

after a valid reference clock is back. For proper HOLD function, the analog PLL lock detect mode has to be

active.

The following register settings are involved with the HOLD function:

•

Lock Detect Window (Word 3, Bit 2, 3, 6): Defines the window in ns inside the lock is valid. The size is

3.5 ns, 8.5 ns, 18.5 ns, or a complete cycle-slip. Lock is set if reference clock and the feedback clock are

inside this predefined lock-detect window for a pre-selected number of successive cycles or if a cycle-slip no

longer occurs.

•

Out-of-Lock: Defines the out-of-lock condition: If the reference clock and the feedback clock at the PFD are

outside the predefined Lock Detect Window or if a cycle-slip occurs.

•

Cycle-Slip (Word 3, Bit 6): Cycle-slip occurs when the phase shift at the PFD is greater than one period of

the frequency. It is a complete (integer number) cycle jump, i.e. caused by an out-of-lock of the PLL.

Cycle-slip is equivalent to the PLL pull-in time.

•

Number of Clock Cycles (Word 3, Bit 4, 5): Defines the number of successive PFD cycles which have to

occur inside the lock window to set Lock detect. This applies not for out-of-lock condition.

•

Hold-Function (Word 3, Bit 9): Selects HOLD function (see more details below).

•

Hold-Trigger (Word 3, Bit 11): Defines whether the HOLD function is always activated (Bit 11 = [1]) or

whether it is dependent on the state of the analog PLL lock detect output (Bit 11 = [0]). In the latter case,

HOLD is activated, if lock is set (high) and de-activated if Lock is reset (low).

•

Analog PLL Lock Detect (Word 1, Bit 29): Analog lock output charges or discharges an external capacitor

with every valid lock cycle. The time constant for Lock detect can be set by the value of the capacitor.

The CDCM7005 supports two types of HOLD functions, one external controllable HOLD mode and one internal

mode, HOLD.

With the external HOLD function the charge pump can directly be switched into 3-state (pin H8 [BGA] or pin 14

[QFN] can be programmed for HOLD [Word 2, Bit 29]). This function is also available via SPI register (Word 2,

Bit 31).

If logic low is applied to the HOLD pin, the charge pump will be switched to 3-state. After the HOLD pin is

released, the charge pump is switched back in to normal operation with the next valid reference clock cycle at

PRI_REF or SEC_REF and the next valid feedback clock cycle at the PFD. During HOLD, the P divider and all

outputs Yx are at normal operation.

HOLD-Over-Function: The PLL has to be in lock to start the HOLD function. It switches the charge pump in to

3-State when an out-of-lock event occurs. It leaves the 3-state charge pump state when the reference clock is

back. Then it starts a locking sequence of 64 cycles before it goes back to the beginning of the HOLD-over loop.

The dedicated looking sequence and a digital phase alignment enable a fast lock.

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