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Output Mode Selection for LVCMOS and LVPECL Outputs: Y0A, Y0B, Y1A

PFD Pulse Width Delay (Word 2)

Lock-Detect Window (Word 3)

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

OUTSELx

OUTxB1

OUTxB0

LVCMOS

OUTxA1

OUTxA0

LVCMOS

Default

[YxB]

[YxA]

LVCMOS

0

0

0

Active

0

0

Active

0

0

1

3-state

0

1

3-state

0

1

0

Inverting

1

0

Inverting

0

1

1

Low

1

1

Low

OUTSELx

OUTxB1

OUTxB0

OUTxA1

OUTxA0

LVCMOS

Default

[YxA]

LVPECL

1

x

x

x

0

Active

Yx

1

x

x

x

1

3-state

(1)

If the differential LVPECL output e.g. Y0A:Y0B is selected (bit 2 of word 1), then only bit 7 of word 1 defines the output mode for

Y0A:Y0B. The settings of bit 8, bit 9, and bit 10 of word 1 are therefore not relevant to the Y0A:Y0B. This applies for the other LVPECL

outputs as well.

DLYM2 / DLYN2

DLYM1 / DLYN1

DLYM0 / DLYN0

Phase Offset

Default

0

0

0

0 ps

Yes

0

0

1

±160 ps

0

1

0

±320 ps

0

1

1

±480 ps

1

0

0

±830 ps

1

0

1

±1130 ps

1

1

0

±1450 ps

1

1

1

±1750 ps

(1)

If Progr. Delay M is set, all Yx outputs are lagging to the reference clock according to the value set. If Progr. If Delay N is set; all Yx

PECL-output relate to Div4 mode.

0

0

1.5 ns

Yes

0

1

3 ns

1

0

4.5 ns

1

1

6 ns

(1)

The PFD pulse width delay gets around the dead zone of the PFD transfer function and reduces phase noise and reference spurs.

(2)

LOCKW1

LOCKW0

Default

0

0

3.5 ns

Yes

0

1

8.5 ns

1

0

18.5 ns

1

1

(1)

(2)

Cycle slip occurs when the phase shift at the PFD is greater than one period of the frequency. It is a complete (integer number) cycle

jump, i.e., cause by a loss-of-lock of the PLL.

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