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B0058-01

PECL

Input

VCXO_IN

VCXO_IN

P Divider

÷ 3

÷ 4

÷ 6

/8

÷ 8

÷ 16

÷ 1

÷ 2

÷ 4

÷ 8

P16-Div

T0065-01

Reference Clock

VCXO Clock

Y-Output div4

Y-Output div4

(90 deg shift)

Y-Output div8

(90 deg shift)

90 deg

90 deg

Y-Output div8

90 deg

90 deg

LVCMOS Outputs

LVPECL Outputs

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

The LVPECL outputs are designed to terminate in to a 50-

Ω load to V

the standard LVCMOS load (see Figure 12). The LVPECL and LVCMOS outputs can be enabled (normal

operation) or disabled (3-state).

In addition, the output phase can be shifted by 90 degrees when using the additional div-by-4 or div-by-8 mode

of the P16-Div (see Figure 20). In the default mode (after power up), the div-by-16 mode of the P16-Div is active.

To change it to a 90 degree phase shift, bit 30 or bit 31 of word 1 has to be programmed accordingly. The P

16-Div has to be selected via the dedicated YxMUX to obtain the 90 degree phase shift. The outputs are

switched in pairs. When selecting the 90 degree phase shift mode, the div-by-16 functions will no longer be

available. The 90 degree phase shifted signal is lagging to the non-shifted signal.

Figure 20. 90 Degree Phase Shift Option of P-Divider

The following diagram shows the LVCMOS and LVPECL output signal when 90 degree phase shift is on.

Figure 21. Output Switching Diagram

In addition, the LVCMOS supports disabled-to-low and 180 degree output phase shift for each output individually.

When selecting the 180 degree phase shift together with the 90 degree phase shift, the respective outputs has a

total phase shift of 270 degree (see Table 2).

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