PIC1F628 datasheet(99/170 Pages) MICROCHIP

99 / 170 page

 2003 Microchip Technology Inc.

Preliminary

DS40300C-page 97

PIC16F62X

14.5.5

TIMEOUT SEQUENCE

On power-up the timeout sequence is as follows: First

PWRT timeout is invoked after POR has expired. Then

OST is activated. The total timeout will vary based on

oscillator configuration and PWRTE bit status. For

example, in ER mode with PWRTE bit erased (PWRT

disabled), there will be no timeout at all. Figure 14-8,

Figure 14-9

and

Figure 14-10

depict

timeout

sequences.

Since the timeouts occur from the POR pulse, if MCLR

is kept low long enough, the timeouts will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 14-9). This is useful for testing purposes or

to synchronize more than one PIC16F62X device

operating in parallel.

Table 14-7 shows the RESET conditions for some

special registers, while Table 14-8 shows the RESET

conditions for all the registers.

14.5.6

POWER CONTROL (PCON) STATUS

The Power Control/STATUS register, PCON (address

8Eh) has two bits.

Bit0 is BOD (Brown-out). BOD is unknown on Power-

on Reset. It must then be set by the user and checked

on subsequent RESETS to see if BOD = 0 indicating

that a brown-out has occurred. The BOD STATUS bit is

a don’t care and is not necessarily predictable if the

brown-out circuit is disabled (by setting BODEN bit = 0

in the Configuration word).

Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent RESET if POR is ‘0’, it will indicate that a

Power-on Reset must have occurred (V

DD may have

gone too low).

TABLE 14-4:

TIMEOUT IN VARIOUS SITUATIONS

TABLE 14-5:

STATUS/PCON BITS AND THEIR SIGNIFICANCE

TABLE 14-6:

SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Oscillator Configuration

Power-up

Brown-out Detect

Reset

Wake-up

from SLEEP

PWRTE = 0

PWRTE = 1

XT, HS, LP

72 ms + 1024 T

OSC

1024 T

OSC

72 ms + 1024 T

OSC

1024 T

OSC

ER, INTRC, EC

72 ms

—

72 ms

—

POR

BOD

0X11

Power-on Reset

0X0X

Illegal, TO is set on POR

0XX0

Illegal, PD is set on POR

10XX

Brown-out Detect Reset

110u

WDT Reset

1100

WDT Wake-up

11uu

MCLR Reset during normal operation

1110

MCLR Reset during SLEEP

Legend: u = unchanged, x = unknown.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR Reset

Value on all

other

RESETS(1)

03h

STATUS

IRP

RP1

RPO

0001 1xxx

000q quuu

8Eh

PCON

—

OSCF

Reset

POR

BOD

---- 1-0x

---- u-uq

Note

1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect Reset and Watchdog Timer Reset during normal opera-

tion.

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