PIC1F628 datasheet(89/170 Pages) MICROCHIP

89 / 170 page

 2003 Microchip Technology Inc.

Preliminary

DS40300C-page 87

PIC16F62X

13.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full V

DD range). This memory

is not directly mapped in the register file space. Instead

it is indirectly addressed through the Special Function

Registers (SFRs). There are four SFRs used to read

and write this memory. These registers are:

•EECON1

• EECON2 (Not a physically implemented register)

•EEDATA

•EEADR

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location

being accessed. PIC16F62X devices have 128 bytes of

data EEPROM with an address range from 0h to 7Fh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write-

time will vary with voltage and temperature as well as

from chip to chip. Please refer to AC specifications for

exact limits.

When the device is code protected, the CPU may

continue to read and write the data EEPROM memory.

The device programmer can no longer access

this memory.

Additional information on the Data EEPROM is

available in the PICmicro™ Mid-Range Reference

Manual, (DS33023).

EEADR REGISTER (ADDRESS: 9Bh)

13.1

EEADR

The EEADR register can address up to a maximum of

256 bytes of data EEPROM. Only the first 128 bytes of

data EEPROM are implemented and only seven of the

eight bits in the register (EEADR<6:0>) are required.

The upper bit is address decoded. This means that this

bit should always be '0' to ensure that the address is in

the 128 byte memory space.

13.2

EECON1 AND EECON2

REGISTERS

EECON1 is the control register with five low order bits

physically implemented. The upper-three bits are non-

existent and read as '0's.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Timeout Reset during normal

operation. In these situations, following RESET, the

user can check the WRERR bit and rewrite the

location. The data and address will be unchanged in

the EEDATA and EEADR registers.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the Data EEPROM write sequence.

R/W

Reserved

EADR6

EADR5

EADR4

EADR3

EADR2

EADR1

EADR0

bit 7

bit 0

bit 7

Unimplemented Address: Must be set to ‘0’

bit 6-0

EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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