PIC1F628 datasheet(57/170 Pages) MICROCHIP

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 2003 Microchip Technology Inc.

Preliminary

DS40300C-page 55

PIC16F62X

The code example in Example 9-1 depicts the steps

required to configure the Comparator module. RA3 and

RA4 are configured as digital output. RA0 and RA1 are

configured as the V- inputs and RA2 as the V+ input to

both comparators.

EXAMPLE 9-1:

INITIALIZING

COMPARATOR MODULE

9.2

Comparator Operation

A single comparator is shown in Figure 9-2 along with

the relationship between the analog input levels and

the digital output. When the analog input at V

IN+ is less

than the analog input V

IN-, the output of the comparator

is a digital low level. When the analog input at V

IN+ is

greater than the analog input V

IN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 9-2 represent

the uncertainty due to input offsets and response time.

9.3

Comparator Reference

An external or internal reference signal may be used

depending on the Comparator Operating mode. The

analog signal that is present at V

IN- is compared to the

signal at V

IN+, and the digital output of the comparator

is adjusted accordingly (Figure 9-2).

FIGURE 9-2:

SINGLE COMPARATOR

9.3.1

EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

comparator module can be configured to have the

comparators operate from the same or different

reference

sources.

However,

threshold

detector

applications may require the same reference. The

reference signal must be between V

SS and VDD, and

can be applied to either pin of the comparator(s).

9.3.2

INTERNAL REFERENCE SIGNAL

The Comparator module also allows the selection of an

internally

generated

voltage

reference

for

the

comparators. Section 10.0, Voltage Reference Manual,

contains a detailed description of the Voltage Refer-

ence module that provides this signal. The internal

reference signal is used when the comparators are in

mode CM<2:0>=010 (Figure 9-1). In this mode, the

internal voltage reference is applied to the V

IN+ pin of

both comparators.

9.4

Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is ensured to have a valid level. If

the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise the

maximum delay of the comparators should be used

(Table 17-1).

FLAG_REG EQU

0X20

CLRF

FLAG_REG

;Init flag register

CLRF

PORTA

;Init PORTA

MOVF

CMCON, W

;Load comparator bits

ANDLW

0xC0

;Mask comparator bits

IORWF

FLAG_REG,F

;Store bits in flag register

MOVLW

0x03

;Init comparator mode

MOVWF

CMCON

;CM<2:0> = 011

BSF

STATUS,RP0

;Select Bank1

MOVLW

0x07

;Initialize data direction

MOVWF

TRISA

;Set RA<2:0> as inputs

;RA<4:3> as outputs

;TRISA<7:5> always read ‘0’

BCF

STATUS,RP0

;Select Bank 0

CALL

DELAY10

;10

µs delay

MOVF

CMCON,F

;Read CMCONtoend changecondition

BCF

PIR1,CMIF

;Clear pending interrupts

BSF

STATUS,RP0

;Select Bank 1

BSF

PIE1,CMIE

;Enable comparator interrupts

BCF

STATUS,RP0

;Select Bank 0

BSF

INTCON,PEIE ;Enable peripheral interrupts

BSF

INTCON,GIE

;Global interrupt enable

–

N+

IN-

Result

IN-

IN+

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