AT89C51ED2-RDTIM datasheet(70/137 Pages) ATMEL

70 / 137 page

AT89C51RD2/ED2

4235E–8051–04/04

Figure 35. SPI Interrupt Requests Generation

Registers

There are three registers in the Module that provide control, status and data storage functions. These registers

are describes in the following paragraphs.

Serial Peripheral Control

•

The Serial Peripheral Control Register does the following:

•

Selects one of the Master clock rates

•

Configure the SPI Module as Master or Slave

•

Selects serial clock polarity and phase

•

Enables the SPI Module

•

Frees the SS pin for a general-purpose

Table 48 describes this register and explains the use of each bit

Table 48. SPCON Register

SPCON - Serial Peripheral Control Register (0C3H)

SSDIS

MODF

CPU Interrupt Request

SPI Receiver/error

CPU Interrupt Request

SPI Transmitter

SPI

CPU Interrupt Request

SPIF

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit Number

Bit Mnemonic

Description

SPR2

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate.

SPEN

Serial Peripheral Enable

Cleared to disable the SPI interface.

Set to enable the SPI interface.

5SSDIS

SS Disable

Cleared to enable SS in both Master and Slave modes.

Set to disable SS in both Master and Slave modes. In Slave mode,

this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF

interrupt request is generated

4MSTR

Serial Peripheral Master

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

3CPOL

Clock Polarity

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle low.

2CPHA

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle

state (see CPOL).

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

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