S29CD032G datasheet(22/93 Pages) SPANSION

22 / 93 page

S29CD032G

30606B0 March 22, 2004

Ad va n c e

In f o rm a t i o n

CE# Control in Linear Mode

The CE# (Chip Enable) pin enables the device during read mode operations. CE#

must meet the required burst read setup times for burst cycle initiation. If CE#

is taken to VIH at any time during the burst linear or burst cycle, the device im-

mediately exits the burst sequence and floats the DQ bus signal. Restarting a

burst cycle is accomplished by taking CE# and ADV# to VIL.

ADV# Control In Linear Mode

The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock

edge when CE# and ADV# are at VIL and the device is configured for either linear

burst mode operation. A burst access is initiated and the address is latched on

the first rising CLK edge when ADV# is active or upon a rising ADV# edge, which-

ever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear

burst sequence, the previous address is discarded and subsequent burst transfers

are invalid until ADV# transitions to VIH before a clock edge, which initiates a new

burst sequence.

RESET# Control in Linear Mode

The RESET# pin immediately halts the linear burst access when taken to VIL. The

DQ data bus signal float. Additionally, the Configuration Register contents are

reset back to the default condition where the device is placed in asynchronous

access mode.

OE# Control in Linear Mode

The OE# (Output Enable) pin is used to enable the linear burst data on the DQ

data bus pin. De-asserting the OE# pin to VIH during a burst operation floats the

data bus. However, the device will continue to operate internally as if the burst

sequence continues until the linear burst is complete. The OE# pin does not halt

the burst sequence, this is accomplished by either taking CE# to VIH or re-issuing

a new ADV# pulse. The DQ bus remains in the float state until OE# is taken to

VIL.

IND/WAIT# Operation in Linear Mode

The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs

the system that the last address of a burst sequence is on the DQ data bus. For

example, if a 2-double-word linear burst access is enabled using a 16-bit DQ bus

(WORD# = VIL), the IND/WAIT# signal transitions active on the second access.

If the same scenario is used, the IND/WAIT# signal has the same delay and setup

timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE# sig-

nal. If OE# is at VIH, the IND/WAIT# signal floats and is not driven. If OE#is at

VIL, the IND/WAIT# signal is driven at VIH until it transitions to VIL indicating the

end of burst sequence. The IND/WAIT# signal timing and duration is (See “Con-

figuration Register” for more information). The following table lists the valid

combinations of the Configuration Register bits that impact the IND/WAIT#

timing.

Table 7. Valid Configuration Register Bit Definition for IND/WAIT#

DOC

Definition

IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on risiong CLD edge

IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge

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