S29CD032G datasheet(33/93 Pages) SPANSION

33 / 93 page

March 22, 2004 30606B0

S29CD032G

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In forma t i o n

6) Executing the Chip Erase command is permitted when the SecSi Sector is en-

abled. The Chip Erase command erases all sectors in the memory array except

for sector 0 in top-bootblock configuration and sector 45 in bottom-bootblock

configuration. The SecSi Sector is a one-time programmable memory area that

cannot be erased.

7) Executing the SecSi Sector Entry command during program or erase suspend

mode is allowed. The Sector Erase/Program Resume command is disabled while

the SecSi sector is enabled, and the user cannot resume programming of the

memory array until the Exit SecSi Sector command is written.

SecSi Sector Protection Bit

The SecSi Sector Protection Bit prevents programming of the SecSi Sector mem-

ory area. Once set, the SecSi Sector memory area contents are non-modifiable.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of

the Password Mode Locking Bit after power-up reset. If the Password Mode Lock-

ing Bit is set, which indicates the device is in Password Protection Mode, the PPB

Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset.

The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to

issue the Password Unlock command. Successful execution of the Password Un-

lock command clears the PPB Lock Bit, allowing for sector PPBs modifications.

Asserting RESET#, taking the device through a power-on reset, or issuing the

PPB Lock Bit Set command sets the PPB Lock Bit back to a “1”.

If the Password Mode Locking Bit is not set, indicating Persistent Sector Protec-

tion Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB

Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means

for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The

Password Unlock command is ignored in Persistent Sector Protection Mode.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during VCC

power-up and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This pro-

tects data during VCC power-up and power-down. The command register and all

internal erase/program circuits are disabled, and the device resets. Subsequent

writes are ignored until VCC is greater than VLKO. The system must provide the

proper signals to the control pins to prevent unintentional writes when VCC is

greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#, or WE# do not initiate a

write cycle.

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