S29CD032G datasheet(19/93 Pages) SPANSION

19 / 93 page

March 22, 2004 30606B0

S29CD032G

Ad va nc e

In forma t i o n

is primarily intended for programming equipment to automatically match a device

to be programmed with its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID on ad-

dress pin A9. Address pins A6, A1, and A0 must be as shown in Table 12 (top boot

devices) or Table 13 (bottom boot devices). In addition, when verifying sector

protection, the sector address must appear on the appropriate highest order ad-

dress bits (see Tables 12 and 13). Table 5 shows the remaining address bits that

are don’t care. When all necessary bits have been set as required, the program-

ming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autose-

lect command via the command. This method does not require VID. See

“Command Definitions” for details on using the autoselect mode.

Table 5. S29CD032G Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20.

Asynchronous Read Operation (Non-Burst)

The device has two control functions which must be satisfied in order to obtain

data at the outputs. CE# is the power control and should be used for device se-

lection. OE# is the output control and should be used to gate data to the output

pins if the device is selected. The device is power-up in an asynchronous read

mode. In the asynchronous mode the device has two control functions which

must be satisfied in order to obtain data at the outputs. CE# is the power control

and should be used for device selection. OE# is the output control and should be

used to gate data to the output pins if the device is selected.

Address access time (tACC) is equal to the delay from stable addresses to valid

output data. The chip enable access time (tCE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output pins. The output enable access

time is the delay from the falling edge of OE# to valid data at the output pins

(assuming the addresses have been stable for at least tACC–tOE time).

Description

CE# OE# WE#

A19

A11

A10

DQ7

DQ0

Manufacturer ID:

FASL

VID

0001h

Read Cycle 1

VID

007Eh

Read Cycle 2

VID

0009h

Read Cycle 3

VID

HHHH

0000h

Ordering Option 00

0001h

Ordering Option 01

PPB Protection Status

VID

LLLLL

0000h (unprotected)

0001h (protected)

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