EL5525 datasheet(2/10 Pages) RENESAS

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EL5525

FN7393 Rev 2.00

Page 2 of 10

September 21, 2010

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Absolute Maximum Ratings (TA = +25°C)

Thermal Information

Supply Voltage

Between VS and GND . . . . . . . . . . . . . . . .4.5V(min) to 18V(max)

Between VSD and GND . . . . . . . . . . . 3V(min) to VS and +7(max)

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

Electrical Specifications

VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = +25°C, unless

otherwise specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

Supply Current

No load

ISD

Digital Supply Current

0.17

0.35

ANALOG

VOL

Output Swing Low

Sinking 5mA (VREFH = 15V, VREFL = 0)

150

VOH

Output Swing High

Sourcing 5mA (VREFH = 15V, VREFL = 0)

14.85

14.95

ISC

Short Circuit Current

RL = 10

100

140

PSRR

Power Supply Rejection Ratio

VS+ is moved from 14V to 16V

Program to Out Delay

4ms

VAC

Accuracy Referred to the Ideal Value

Code = 512

VMIS

Channel to Channel Mismatch

Code = 512

VDROOP

Droop Voltage

mV/ms

RINH

Input Resistance @ VREFH, VREFL



REG

Load Regulation

IOUT = 5mA step

0.5

1.5

mV/mA

Band Gap

1.1

1.3

1.6

DIGITAL

VIH

Logic 1 Input Voltage

VIL

Logic 0 Input Voltage

FCLK

Clock Frequency

5MHz

Setup Time

Hold Time

tLC

Load to Clock Time

tCE

Clock to Load Line

tDCO

Clock to Out Delay Time

Negative edge of SCLK

RSDIN

SDIN Input Resistance



TPULSE

Minimum Pulse Width for EXT_OSC

Signal

5µs

Duty Cycle

Duty Cycle for EXT_OSC Signal

F_OSC

Internal Refresh Oscillator Frequency

OSC_Select = 0

kHz

INL

Integral Nonlinearity Error

1.3

LSB

DNL

Differential Nonlinearity Error

0.5

LSB

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