EL5525

FN7393 Rev 2.00

Page 7 of 10

September 21, 2010

Block Diagram

Channel Outputs

Each of the channel outputs has a rail-to-rail buffer. This

enables all channels to have the capability to drive to within

50mV of the power rails, (see Table Electrical Specifications

on page 2 for details).

When driving large capacitive loads, a series resistor should

be placed in series with the output. (Usually between 5

 and

50

).

Each of the channels is updated on a continuous cycle, the

time for the new data to appear at a specific output will

depend on the exact timing relationship of the incoming data

to this cycle.

The best-case scenario is when the data has just been

captured and then passed on to the output stage

immediately; this can be as short as 48µs. In the worst-case

scenario, this will be 860µs for EL5525, when the data has

just missed the cycle at f_OSC = 21kHz.

When a large change in output voltage is required, the

change will occur in 2V steps, thus the requisite number of

timing cycles will be added to the overall update time. This

means that a large change of 16V can take between 6.8ms

and 7.2ms depending on the absolute timing relative to the

update cycle.

Output Stage and the Use of External

Oscillator

in Figure 7. The refreshed switches are controlled by the

internal or external oscillator signal. When the OSC clock

CH is being charged. When the OSC clock signal is high, the

voltage is maintained by CH. This refreshed process will

repeat every 18 clock cycles for each channel. The time

VOLTAGE

SOURCES

18

CHANNEL

REGISTERS

CONTROL IF

SDI

SCLK

ENA

EXT_OSC

SDO

CAP

REFL

OUTR

OUTQ

OUTP

OUTE

OUTD

OUTC

OUTB

OUTA

REFH

OSC_SELECT

-

+

1.3V

FIGURE 7. SIMPLIFIED OUTPUT SAMPLE AND HOLD AMP

STAGE FOR ONE CHANNEL

-

+

-

+

CH

OSC

1.3V