EL5525

FN7393 Rev 2.00

Page 6 of 10

September 21, 2010

Analog Section

Transfer Function

The transfer function is: shown in Equaion 1:

where data is the decimal value of the 10-bit data binary

input code.

The output voltages from the EL5525 will be derived from

pins. The impedance between those two pins is about 32k

.

Care should be taken that the system design holds these two

reference voltages within the limits of the power rails of the

Clock Oscillator

The EL5525 requires an internal clock or external clock to

refresh its outputs. The outputs are refreshed at the falling OSC

clock edges. The output refreshed switches open at the rising

edges of the OSC clock. The driving load shouldn’t be changed

at the rising edges of the OSC clock. Otherwise, it will generate

a voltage error at the outputs. This clock may be input or output

via the clock pin labeled EXT_OSC. The internal clock is

provided by an internal oscillator running at approximately

21kHz and can be output to the EXT_OSC pin. In a 2 chip

system, if the driving loads are stable, one chip may be

programmed to use the internal oscillator; then the OSC pin will

output the clock from the internal oscillator. The second chip

may have the OSC pin connected to this clock source.

For transient load application, the external clock Mode

should be used to ensure all functions are synchronized

together. The positive edge of the external clock to the OSC

pin should be timed to avoid the transient load effect. The

Application Drawing shows the LCD H rate signal used, here

the positive clock edge is timed to avoid the transient load of

the column driver circuits.

After power on, the chip will start with the internal oscillator

mode. At this time, the EXT_OSC pin will be in a high

impedance condition to prevent contention. By setting pin 10

to high, the chip is on external clock mode. Setting pin 10 to

low, the chip is on internal clock mode.

TABLE 2. SERIAL TIMING PARAMETERS

PARAMETER

RECOMMENDED OPERATING RANGE

DESCRIPTION

T

200ns

Clock Period

0.05 * T

Clock Rise/Fall Time

10ns

ENA Hold Time

10ns

ENA Setup Time

10ns

Data Hold Time

10ns

Data Setup Time

0.50 * T

Clock Pulse Width

TABLE 3. SERIAL PROGRAMMING EXAMPLES

Control

Channel Address

Data

Condition

C1

A4

A3

A2

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

00

000

0000

000

00

Channel A, Value = 0

0

0

00

001

1111

111

11

Channel A, Value = 1023

0

0

00

001

0000

000

00

Channel A, Value = 512

0

0

00

111

0000

000

01

Channel C, Value = 513

0

0

01

110

0000

111

11

Channel H, Value = 31

0

1

00

010

0000

111

11

Channel R, Value = 31



=

data

1024

-------------





+

(EQ. 1)