MP6528 – 5V TO 60V, H-BRIDGE GATE DRIVER

MP6528 Rev. 1.03

www.MonolithicPower.com

12

6/20/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2017 MPS. All Rights Reserved.

exceeds the voltage supplied to the OCREF

terminal, a short circuit is recognized.

In the event of a short circuit, the MP6528

disables all of the gate drive outputs. nFAULT is

driven active low. The device will stay latched off

until it is reset by nSLEEP or VIN UVLO.

Short circuit protection can be disabled by

connection a 100k

Ω resistor from VREG to the

OCREF pin.

Over-current Protection (OCP)

The MP6528 can implement output overcurrent

protection (OCP) by monitoring the current

through a low-side shunt resistor connected to

the

low-side

MOSFETs.

This

resistor

is

connected to the LSS input pin and the low-side

MOSFET source terminals. If the OCP function

is not desired, the LSS pin and MOSFET source

terminals should all be connected directly to

ground.

If the LSS voltage (the voltage across the shunt

resistor) exceeds the LSS OCP threshold voltage

OCP event is detected, the MP6528 will enter a

latched fault state and disable all functions. The

device will stay latched off until it is reset by

nSLEEP or VIN UVLO.

The OCP current limit level is selected by the

value of the current sense resistor at LSS pin.

Refer to the applications information section for

more information.

OCP protection can be disabled by connection a

100k

Ω resistor from VREG to the OCREF pin.

Short-circuit and OCP Deglitch Time

There is often a current spike during switching

transitions, due to body diode reverse-recovery

current or the distributed capacitance of the load.

This current spike requires filtering to prevent it

from erroneously triggering OCP. An internal

VDS monitor when the outputs are switched.

Dead-Time Adjustment

To prevent shoot-through in any phase of the

between a high- or low-side turn-off and the next

complementary turn-on event. The dead time for

both phases is set by a single dead-time resistor

(1)

If DT is tied to directly to ground, an internal

minimum dead time (30ns) will be applied.

Leaving DT open generates approximately a 6µs

dead time.

UVLO Protection

If at any time the voltage on VIN falls below the

undervoltage

lockout

threshold

all

circuitry in the device is disabled and the internal

logic will be reset.

Operation

will

resume

with

the

power-up

sequence when VIN rises above the UVLO

thresholds.

After power-up, if the voltage on VREG drops

below the V

enter a latched fault state and disable all

functions. The nFAULT pin will be driven active

low.

The device will stay latched off until it is

reset by nSLEEP or VIN UVLO.

Thermal Shutdown

If the die temperature exceeds safe limits, the

MP6528 will enter a latched fault state and

disable all functions. The device will stay latched

off until it is reset by nSLEEP or VIN UVLO.