ISL6569ACR datasheet(17/22 Pages) RENESAS

17 / 22 page

ISL6569A

FN9092 Rev 2.00

Page 17 of 22

Dec 29, 2004

Load-Line Regulation Resistor

The load-line regulation resistor is labeled RFB in Figure 6.

Its value depends on the desired full-load droop voltage

(VDROOP in Figure 6). If Equation 19 is used to select each

ISEN resistor, the load-line regulation resistor is as shown

in Equation 21.

If one or both of the ISEN resistors was adjusted for thermal

balance, as in Equation 20, the load-line regulation resistor

should be selected according to Equation 22. Where IFL is

the full-load operating current and RISEN(n) is the ISEN

resistor connected to the nth ISEN pin.

Output Filter Design

The output inductors and the output capacitor bank

together form a low-pass filter responsible for smoothing

the pulsating voltage at the phase nodes. The output filter

also must provide the transient energy during the interval of

time after the beginning of the transient until the regulator

can respond. Because it has a low bandwidth compared to

the switching frequency, the output filter necessarily limits

the system transient response leaving the output capacitor

bank to supply or sink load current while the current in the

output inductors increases or decreases to meet the

demand.

In high-speed converters, the output capacitor bank is

usually the most costly (and often the largest) part of the

circuit. Output filter design begins with minimizing the cost of

this part of the circuit. The critical load parameters in

choosing the output capacitors are the maximum size of the

load step,

I; the load-current slew rate, di/dt; and the

maximum allowable output-voltage deviation under transient

loading,

VMAX. Capacitors are characterized according to

their capacitance, ESR, and ESL (equivalent series

inductance).

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the

voltage drop across the ESR increases linearly until the

load current reaches its final value. The capacitors selected

must have sufficiently low ESL and ESR so that the total

output-voltage deviation is less than the allowable

maximum. Neglecting the contribution of inductor current

and regulator response, the output voltage initially deviates

by an amount

The filter capacitor must have sufficiently low ESL and ESR

so that

V < VMAX.

Most capacitor solutions rely on a mixture of high-frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance, but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor ac ripple current (see Interleaving and

Equation 2), a voltage develops across the bulk-capacitor

ESR equal to IC,PP (ESR). Thus, once the output capacitors

are selected, the maximum allowable ripple voltage,

VPP(MAX), determines the lower limit on the inductance.

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

VMAX. This places an upper limits on inductance.

Equation 26 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 25

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, and C is the total output capacitance.

Compensation

The two opposing goals of compensating the voltage

regulator are stability and speed. Depending on whether the

regulator employs the optional load-line regulation as

described in Load-Line Regulation, there are two distinct

methods for achieving these goals.

RFB

VDROOP

50 10

–



-------------------------

(EQ. 21)

RFB

VDROOP

IFL rDS ON



--------------------------------

RISEN n





(EQ. 22)

V

ESL

 di

-----ESR

 I



(EQ. 23)

ESR



VIN 2VOUT

–



 V

OUT

fSVINVPP MAX



----------------------------------------------------------



(EQ. 24)

4CVO

I

2

----------------

V

MAX

IESR



–



(EQ. 25)

2.5

C

I

2

-----------------

V

MAX

IESR



–

VIN VO

–







(EQ. 26)

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