ISL6569ACR datasheet(12/22 Pages) RENESAS

12 / 22 page

ISL6569A

FN9092 Rev 2.00

Page 12 of 22

Dec 29, 2004

LOAD-LINE REGULATION

Microprocessor load current demands change from near no-

load to full load often during operation. The resulting sizable

transient current slew rate causes an output voltage spike

since the converter is not able to respond fast enough to the

rapidly changing current demands. The magnitude of the

spike is dictated by the ESR and ESL of the output

capacitors selected. In order to drive the cost of the output

capacitor solution down, one commonly accepted approach

is active voltage positioning. By adding a well controlled

output impedance, the output voltage can effectively be level

shifted in a direction which works against the voltage spike.

The average current of all the active channels, IAVG, flows out

IOUT, see Figure 6. IOUT is connected to FB through a load-

line regulation resistor, RFB. The resulting voltage drop across

RFB is proportional to the output current, effectively creating

an output voltage droop with a steady-state value defined as

In most cases, each channel uses the same RISEN value to

sense current. A more complete expression for VDROOP is

derived by combining Equations 4 and 5.

Droop is an optional feature of the ISL6569A. If active voltage

positioning is not required, simply leave the IOUT pin open.

REFERENCE OFFSET

Typical microprocessor tolerance windows are centered

around a nominal DAC set point. Implementing a load-line

requires offsetting the output voltage above this nominal

DAC set point; centering the load-line within the static

specification window. The ISL6569A features an internal

100

A current source which feeds out the OFS pin. Placing

a resistor from OFS and ground allows the user to set the

amount of positive offset desired directly to the reference

voltage. The voltage developed across the OFS resistor,

ROFS, is divided down internally by a factor of 10 and

directly counters the DAC voltage at the error amplifier non-

inverting input. Select the resistor value based on the

voltage offset desired, VOFS, using Equation 7

DYNAMIC VID

Next generation microprocessors can change VID inputs at

any time while the regulator is in operation. The power

management solution is required to monitor the DAC inputs

and respond to VID voltage transitions, or ‘on-the-fly’ VID

changes, in a controlled manner. Supervising the safe output

voltage transition within the DAC range of the processor

without discontinuity or disruption.

The ISL6569A checks the five VID inputs at the beginning of

each channel-1 switching cycle. If the VID code has

changed, the controller waits one complete switching cycle

to validate the new code. If the VID code is stable for this

entire switching cycle, then the controller will begin

executing the output voltage change. The controller begins

incrementing the reference voltage by making 25mV steps

every two switching cycles until it reaches the new VID code.

The total time required for a VID change, tDV, is dependent

on the switching frequency (fS), the size of the change

(

VID), and the time before the next switching cycle begins.

Since the ISL6569A recognizes VID-code changes only at

the beginning of switching cycles, up to one full cycle may

pass before a VID change registers. This is followed by a

one-cycle wait before the output voltage begins to change.

The one-cycle uncertainty in Equation 8 is due to the

possibility that the VID code change may occur up to one full

cycle before being recognized.

The time required for a converter running with fS = 500kHz

to make a 1.2V to 1.4V reference-voltage change is between

s and 32s as calculated using Equation 8. This example

is also illustrated in Figure 7.

1010

0.900

1011

0.875

1100

0.850

1101

0.825

1110

0.800

1111

Shutdown

TABLE 1. VOLTAGE IDENTIFICATION CODES

(Continued)

VID4

VID3

VID2

VID1

VID0

DAC

VDROOP

IAVG RFB

(EQ. 5)

VDROOP

IOUT

-------------

rDS ON



RISEN

---------------------- RFB

(EQ. 6)

ROFS

VOFS 10



100

A

---------------------------

(EQ. 7)

----- 2 VID



0.025

------------------ 1

–





tDV

----- 2 VID



0.025

------------------







(EQ. 8)

FIGURE 7. DYNAMIC-VID WAVEFORMS FOR 500kHz ISL6569A

BASED MULTI-PHASE BUCK CONVERTER

s/DIV

VREF, 100mV/DIV

VOUT, 100mV/DIV

1.2V

VID, 5V/DIV

01110

00110

1.2V

VID CHANGE OCCURS

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