ISL6569ACR datasheet(11/22 Pages) RENESAS

11 / 22 page

ISL6569A

FN9092 Rev 2.00

Page 11 of 22

Dec 29, 2004

Voltage Regulation

The output of the error amplifier, VCOMP, is compared to the

sawtooth waveform to modulate the pulse width of the PWM

signals. The PWM signals control the timing of the Intersil

MOSFET drivers and regulate the converter output to the

specified reference voltage. Three distinct inputs to the error

amplifier determine the voltage level of VCOMP. The internal

and external circuitry which control voltage regulation is

illustrated in Figure 6.

Most multi-phase controllers simply have the output voltage

fed back to the inverting input of the error amplifier through a

resistor. The ISL6569A features an internal differential

remote-sense amplifier in the feedback path. The amplifier

removes the voltage error encountered when measuring the

output voltage relative to the local controller ground

reference point, resulting in a more accurate means of

sensing output voltage. Connect the microprocessor sense

pins to the non-inverting input, VSEN, and inverting input,

RGND, of the remote-sense amplifier. The remote-sense

amplifier output, VDIFF, is then tied through an external

resistor to the inverting input of the error amplifier.

A digital to analog converter (DAC) generates a reference

voltage based on the state of logic signals at pins VID4

through VID0. The DAC decodes the a 5-bit logic signal

(VID) into one of the discrete voltages shown in Table 1.

Each VID input offers a 20

A pull-up to an internal 2.5V

source for use with open-drain outputs. External pull-up

resistors or active-high output stages can augment the pull-

up current sources, but a slight accuracy error can occur if

they are pulled above 2.9V. The DAC-selected reference

voltage is connected to the non-inverting input of the error

amplifier.

The ISL6569A features a second non-inverting input to the

error amplifier which allows the user to directly offset the

DAC reference voltage in the positive direction only. The

offset voltage is created by an internal current source which

feeds out the OFS pin into a user selected external resistor

to ground. The resulting voltage across the resistor, VOFS, is

internally divided down by ten to create the offset voltage.

This method of offsetting the DAC voltage is more accurate

than external methods of level-shifting the FB pin.The

integrating compensation network shown in Figure 6

assures that the steady-state error in the output voltage is

limited to the error in the reference voltage (output of the

DAC) plus offset errors in the OFS current source, remote-

sense and error amplifiers. Intersil specifies the guaranteed

tolerance of the ISL6569A to include all variations in current

sources, amplifiers and the reference so that the output

voltage remains within the specified system tolerance of

±0.5% over temperature.

FIGURE 6. OUTPUT-VOLTAGE AND LOAD-LINE REGULATION

IAVG

REFERENCE

EXTERNAL CIRCUIT

ISL6569A INTERNAL CIRCUIT

COMP

RFB

IOUT

VDIFF

VSEN

RGND

VDROOP

ERROR AMPLIFIER

VOUT

SENSE

GND

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

VOLTAGE

VCOMP

OFS

x0.1

100

A

ROFS

OFFSET

VOLTAGE

VOFS

REMOTE

POINTS

TABLE 1. VOLTAGE IDENTIFICATION CODES

VID4

VID3

VID2

VID1

VID0

DAC

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

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