CMV2000 datasheet(22/64 Pages) AMSCO

22 / 64 page

Reference: CMV2000-datasheet-v3.8

CMV2000 v3 Datasheet

Page 21 of 63

4 READING OUT THE SENSOR

4.1 LVDS DATA OUTPUTS

The CMV2000 has LVDS (low voltage differential signaling) outputs to transport the image data to the surrounding

system. Next to 16 data channels, the sensor also has two other LVDS channels for control and synchronization of the

image data. In total, the sensor has 18 LVDS output pairs (2 pins for each LVDS channel):



16 Data channels



1 Control channel



1 Clock channel

This means that a total of 36 pins of the CMV2000 are used for the LVDS outputs (32 for data + 2 for LVDS clock + 2 for

control channel). See the pin list for the exact pin numbers of the LVDS outputs.

The 16 data channels are used to transfer the 10-bit or 12-bit pixel data from the sensor to the receiver in the

surrounding system.

The output clock channel transports a clock, synchronous to the data on the other LVDS channels. This clock can be

used at the receiving end to sample the data. This clock is a DDR clock which means that the frequency will be half of

the output data rate. When 480Mbps output data rate is used, the LVDS output clock will be 240MHz.

The data on the control channel contains status information on the validity of the data on the data channels. Information

on the control channel is grouped in 10-bit or 12-bit words that are transferred synchronous to the 16 data channels.

4.2 LOW-LEVEL PIXEL TIMING

Figure 18 and Figure 19 show the timing for transfer of 10-bit and 12-bit pixel data over one LVDS output. To make the

timing more clear, the figures show only the p-channel of each LVDS pair. The data is transferred LSB first, with the

transfer of bit D0 during the high phase of the DDR output clock OUTCLK.

OUTCLK_P

OUTX_P

FIGURE 18: 10-BIT PIXEL DATA ON AN LVDS CHANNEL

The time ‘T1’ in Figure 18 is 1/10th of the period of the CLK_IN input clock. If a frequency of 48MHz is used for CLK_IN

(max in 10-bit mode), this results in a 240MHz OUTCLK frequency.

D10 D11

OUTCLK_P

OUTX_P

FIGURE 19: 12-BIT PIXEL DATA ON AN LVDS CHANNEL

The time ‘T2’ in Figure 19 is 1/12th of the period of the CLK_IN input clock. When a frequency of 40MHz is used for

CLK_IN (max in 12-bit mode), this results in a 240MHz OUTCLK frequency.

CMV2000 датащи(PDF) 22 Page - ams AG