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LTC4366 датащи(PDF) 5 Page - Linear Technology

номер детали LTC4366
подробное описание детали  High Voltage Surge Stopper
PDF  24 Pages
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
Logo LINER - Linear Technology

LTC4366 датащи(HTML) 5 Page - Linear Technology

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LTC4366
436612fe
For more information www.linear.com/LTC4366
5
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. All voltages relative to VSS, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FB, SD, TIMER
VFB(REG)
3% FB pin Regulation Threshold (OUT – FB)
l
1.193
1.23
1.267
V
IFB
FB Pin Leakage Current
OUT – FB = 1.2V
l
0
±1
µA
VSD(TH)
SD Pin Threshold Voltage (VDD – SD)
Falling
l
1.0
1.5
2.3
V
VSD(HYST)
SD Pin Hysteresis
LTC4366C/I/H
LTC4366MP
l
l
147
129
280
280
530
530
mV
mV
ISD
SD Pin Input Pull-Up Current
VDD – SD = 0.7V
LTC4366C/I/H
LTC4366MP
l
l
–0.7
–0.5
–1.6
–1.6
–3.5
–3.5
µA
µA
VTIMER(H)
TIMER Pin Threshold
TIMER Rising, VDD = 7V, OUT = VZ(OUT) l
2.6
2.8
3.1
V
ITIMER(UP)
TIMER Pin Pull-Up Current
TIMER = 1V
LTC4366C/I/H
LTC4366MP
l
l
–5.1
–4
–9
–9
–13
–13
µA
µA
ITIMER(DN)
TIMER Pin Pull-Down Current
TIMER = 1V
LTC4366C/I/H
LTC4366MP
l
l
0.9
0.7
1.8
1.8
2.8
2.8
µA
µA
ITIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP)
l
15
20
25
%
AC Characteristics
tDLY SD
SD Low to Gate Low Filter Time
Step VDD – SD from 0V to 3V
l
420
700
1200
µs
tDLY FAST
FB Low to Gate Low Delay Time
Step OUT – FB from 0V to 1.3V
l
60
150
300
ns
tD(COOL)
Cool-Down Timer (Internal)
VDD = VZ(VDD)
LTC4366C/I/H
LTC4366MP
l
l
5.9
5.9
9
9
16
19
Seconds
Seconds
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive.
Note 3: Limits on the maximum rating is defined as whichever limit occurs
first. An internal clamp limits the GATE pin to a maximum of 12V above
source. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the formula:
TJ = TA + (PD • θJA)



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