LTC4366 datasheet(8/24 Pages) LINER

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LTC4366

436612fe

For more information www.linear.com/LTC4366

PIN FUNCTIONS

BASE: Base Driver Output for External PNP Shunt Regula-

tor. This pin is connected to the anode of an internal 6.2V

Zener with the cathode tied to OUT. In cases where lower

Zener (Z3) clamp current is desired but a large VSS resis-

tor is prohibited, connect an external PNP base to this pin

(PNP collector is grounded, emitter is tied to VSS). Tie this

pin to VSS if unused.

Exposed Pad: The exposed pad may be left open or con-

nected to VSS.

FB: Overvoltage Regulation Amplifier Feedback Input.

Connect this pin to an external resistive divider from OUT

to ground. The overvoltage regulation amplifier controls

the gate of the external N-channel MOSFET to regulate

the FB pin voltage at 1.23V below OUT. The overvoltage

amplifier will activate a 200mA pull-down on the GATE pin

during a fast overvoltage event.

GATE: Gate Drive for External N-Channel MOSFET. Dur-

ing start-up an internal 7.5µA current source charges the

gate of the external N-channel MOSFET from the VDD pin.

Once the OUT voltage is above VSS by 4.75V, the charge

pump will finish charging the GATE to 12V above OUT.

During a fast overvoltage event, a 200mA pull-down cur-

rent source between GATE and OUT is activated, followed

by regulation of the GATE pin voltage by the overvoltage

regulation amplifier.

OUT: Charge Pump and Overvoltage Regulation Amplifier

SupplyVoltage.Supplyinputforfloatingcircuitrypowered

from the MOSFET source. Once the OUT voltage is 4.75V

(UVLO2)aboveVSS,thechargepumpwillturnonanddraw

power from this pin. When OUT exceeds 2.55V (UVLO1)

it is used as a power supply and reference input for over-

voltage regulation amplifier. This pin is clamped at 5.7V

and requires a 0.22µF or greater bypass to the VSS pin.

SD: Shutdown Comparator Input. Tie to VDD if unused.

Connectpintoalimitedcurrentpulldowncreatedbyadding

a resistor in series with an open-drain or open-collector

pull-down transistor. Activating the external pull down

overcomes the internal 1.6µA pull-up current source and

allows the SD pin to cross the shutdown threshold. This

threshold is defined as 1.5V below VDD with a 280mV

hysteresis. To prevent false triggers this pin must stay

below the threshold for 700µs to activate the shutdown

state. The shutdown state lowers the total quiescent cur-

rent (IVDD plus IOUT) below 20µA. This quiescent current

does not include shunt current in the VDD, OUT and BASE

regulators. After a fault on the LTC4366, putting the part

in shutdown will clear the fault and allow operation to

resume. Clearing the fault during the 9-second cool-down

period will shorten the timeout for the LTC4366-2 (auto-

retry) version.

TIMER:TimerInput.Leavethispinopenfora1µsovervolt-

age regulation period before fault off. Connect a capacitor

between this pin and VSS to set a 311ms/µF duration for

overvoltage regulation before the switch is turned off.

The LTC4366-2 version will restart after a nine second

cool-down period.

VDD: Start-Up Supply. Supply input for 7.5µA start-up cur-

rent source that charges the gate of the external N-channel

MOSFET. Also provides supply for timer and logic circuits

activewhentheexternalMOSFETisoff.Thispinisclamped

at 12V above VSS. Do not bypass this pin with a capacitor.

VSS: Device Return and Substrate. The capacitors on the

TIMER and OUT pins should be returned to this pin.

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