LTC4366 datasheet(14/24 Pages) LINER

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LTC4366

436612fe

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APPLICATIONS INFORMATION

pin, and finally the current from the VSS pin (see Figure 5).

VIN(MIN) = (IVDD • RIN) + VD + VTH + VC1 + (IVSS • RSS)

Using the Electrical Characteristics table for above

parameters:

VC1 = VUVLO2 = 4.75V (UVLO2 threshold)

IVDD = IVDD(STHI) = 9µA (IVDD start-up, gate high)

IVSS = IVSS(AMP) = 45µA (IVSS w/regulation amp)

VD = 0.58V

VIN(MIN)=(9µA•RIN)+0.58V+VTH+4.75V+(45µA • RSS)

When the MOSFET gate is fully enhanced, the OUT pin

voltage is equal to the supply voltage. This places another

constraint on the minimum supply voltage because the

charge pump increases the VSS current to 160µA. The C1

voltage is assumed to be clamped at 5.7V. These values

are specified as VZ(OUT) and IVSS(CP) (charge pump on)

in the table of Electrical Characteristics:

VIN(MIN) = VZ(OUT) + (IVSS(CP) • RSS)

VIN(MIN) = 5.7V + (160µA • RSS)

The last VIN(MIN) equation sets the maximum value for

RSS. After choosing RSS the maximum value for RIN (for

that particular RSS) is calculated from the first VIN(MIN)

equation:

RSS(MAX) =

VIN(MIN) – 5.7V

160µA

RIN(MAX) =

VIN(MIN) – 4.75V – 0.58V – VTH – 45µA •RSS

(

)

9µA

These two equations maximize the values of RSS and

RIN (reducing power dissipation) while still providing

the necessary VC1 voltage to turn the charge pump on.

Increasing the supply voltage beyond the minimum sup-

ply voltage increases the current and power in RSS while

reducing the time required to charge C1. Conditions that

may require an even smaller RSS(MAX) will be discussed

in the Maximum Supply Start-Up section.

Maximum Supply Start-Up

The maximum overvoltage supply may also exist during

start-up. The overvoltage protection circuitry has to wake

up before high voltage is passed to the load. Dynamically

the GATE is ramping up while C1 is charging. Capacitor

C1 must charge to the 2.55V UVLO1 threshold to turn on

the regulation amplifier and reference before the OUT pin

voltage exceeds the overvoltage regulation point, VREG.

These conditions may reduce the value of RSS below the

maximum value dictated by the minimum supply start-up

discussed above.

When current in RSS exceeds the current sourced from

the VSS pin (essentially IRIN), the capacitor C1 begins to

charge. The voltage at the VSS pin when IRIN = IRSS is now

labeled VSS(MATCH). The VSS pin voltage is the center of a

voltage divider between RIN and RSS after the Zener clamp

voltage from VDD to VSS is subtracted from the supply.

VSS(MATCH) =

RSS

RSS +RIN

• VIN(MAX) – VZ(VDD)

(

)

As VIN increases the VSS(MATCH) voltage increases. If the

match voltage exceeds the overvoltage regulation point

(VREG), then load is unprotected. This is true because

C1 will still need to charge to 2.55V while VSS already

GATE

7.5µA

VDD

RIN

IRIN

VIN

5.7V

12V

IBIAS

ISHUNT2

9µA

ISHUNT1

IC1

IRSS

VOUT

OUT

RLOAD

436612 F05

RSS

VSS

CIRCUITS

LOGIC

TIMER

VC1

–

Figure 5. Simplified Block Diagram

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