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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS7615 датащи(PDF) 19 Page - Cirrus Logic |
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CS7615 датащи(HTML) 19 Page - Cirrus Logic |
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19 / 36 page  CS7615 DS231PP6 19 AGC Maximum Gain Register (2Ah) MGN Sets the maximum gain allowable if the user chooses to limit the chip gain beyond a certain value. The range is 0-242, with the actual max gain word being twice this value. Default is F2h. AGC Slew and Speed Register (2Bh) SLEW Sets the rate of decay of gain when the gain target is exceeded in the maximum intensity bin. Default is 0h. 00 = -8 10 = -32 01 = -16 11 = -64 SPD Varies the AGC loop gain. The error signal used for correction is multiplied by the speed num- ber before being added to the accumulator. Default is 0h. 00 = 1x 10 = 4x 01 = 2x 11 = 8x AGC Minimum Gain Register (2Ch) MNGN Sets the minimum gain allowable if the user chooses to limit the chip gain from a certain value. Default is 00h. CCD Signal Alignment Register (2Dh) These signals adjust the edges of H1 or FR with respect to the internal sampling clock. HR Adjusts the location of the rising edge of H1. HF Adjusts the location of the falling edge of H1. FRR Adjusts the location of the rising edge of FR. FRF Adjusts the location of the falling edge of FR. 76543210 mgn7 mgn6 mgn5 mgn4 mgn3 mgn2 mgn1 mgn0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res slew1 slew0 spd1 spd0 rrrr r/w r/w r/w r/w 76543210 mng7 mng6 mng5 mng4 mng3 mng2 mng1 mng0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 HR1 HR0 HF1 HF0 FRR1 FRR0 FRF1 FRF0 r/w r/w r/w r/w r/w r/w r/w r/w |
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