CS7615 datasheet(17/36 Pages) CIRRUS

17 / 36 page

CS7615

DS231PP6

Software Reset Register (00h)

SR4

Setting bit SR4 to logic high will initiate a CS7615 software reset. Software reset resets all the

digital blocks except for I2C and the ADC calibration logic. The clocks remain running. This reset

bit automatically clears.

Low Power Register (20h)

PD4

Setting bit PD4 to logic high will place the CS7615 chip in a low power mode. The I2C interface

and clock generation circuitry will remain powered up.

Operational control #1 Register (24h)

PAL

Logic high indicates a PAL standard camera system, logic low indicates NTSC. Default = 0.

AGCW

Used to window the portion of the frame to use for AGC. Default = 00.

00 = use entire frame

01 = use center 1/4 area of frame

10 = use center 1/16 area of frame

11 = reserved

AGCDI

Logic high disables CS7615’s automatic gain control circuitry. User may manually control gain

through the gain register 25h/26h. Default = 0.

AGCALG

Controls data used in CS7615’s AGC loop. Logic high indicates mosaic data, logic low indicates

luma data. Default = 0.

CCDTYP

Logic high signifies that a Type B CCD is being used, logic low signifies a Type A CCD. Default

= 0.

FLCKLS

Logic high restricts shutter to flickerless settings. Default = 0.

PALENV

Logic high when the camera system is being used in a PAL environment, logic low in an NTSC

environment. Default = 0.

R/W

Read/Write

Read

WWrite

RES

Reserved

76543210

res

SR4

res

rrr

rrrr

76543210

res

PD4

res

rrr

r/w

rrrr

76543210

PAL

AGCW1

AGCW2

AGCDIS

AGCCALG

CCDTYP

FLCKLS

PALENV

r/w

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