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Automotive PSoC® 4: PSoC 4100

Family Datasheet

Document Number: 001-93576 Rev. *F

Page 10 of 37

Power

The following power system diagram shows the minimum set of

power supply pins as implemented for the PSoC 4100. The

system has one regulator in Active mode for the digital circuitry.

There is no analog regulator; the analog circuits run directly from

the VDDA input. There are separate regulators for the Deep Sleep

and Hibernate (lowered power supply and retention) modes.

There is a separate low-noise regulator for the bandgap. The

supply voltage range is 1.71 to 5.5 V with all functions and

circuits operating over that range.

Figure 4. PSoC 4 Power Supply

The PSoC 4100 family allows two distinct modes of power supply

operation: Unregulated External Supply, and Regulated External

Supply modes.

Unregulated External Supply

In this mode, PSoC 4100 is powered by an External Power

Supply that can be anywhere in the range of 1.8 V to 5.5 V. This

range is also designed for battery-powered operation, for

instance, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of the PSoC 4100 supplies the internal logic and the

VCCD output of the PSoC 4100 must be bypassed to ground via

an external Capacitor (in the range of 1 to 1.6 µF; X5R ceramic

or better).

Bypass capacitors must be used from VDDD to ground, typical

practice for systems in this frequency range is to use a capacitor

in the 1-µF range in parallel with a smaller capacitor (0.1 µF for

example). Note that these are simply rules of thumb and that, for

critical applications, the PCB layout, lead inductance, and the

Bypass capacitor parasitic should be simulated to design and

obtain optimal bypassing.

An example of a bypass scheme for the 28-pin SSOP package

follows.

Figure 5. 28-Pin SSOP Example

Regulated External Supply

In this mode, the PSoC 4100 is powered by an external power

supply that must be within the range of 1.71 to 1.89 V (1.8 ± 5%);

note that this range needs to include power supply ripple too. In

this mode, VCCD, and VDDD pins are all shorted together and

bypassed. The internal regulator is disabled in firmware.

1.8 Volt

Reg

VDDD

VSSD

VDDD

VCCD

Digital

Domain

Table 1. Example of a bypass scheme

Power Supply

Bypass Capacitors

VDDD–VSS

0.1 µF ceramic capacitor (C2) plus bulk

capacitor 1 to 10 µF (C1). Total

Capacitance may be greater than 10 µF.

VCCD–VSS

1 µF ceramic capacitor at the VCCD pin

(C3)

VREF–VSS

(optional)

The internal bandgap may be bypassed

with a 1 µF to 10 µF capacitor. Total capac-

itance may be greater than 10 µF.

(GPIO) P3[0]

( GPIO) P0[1]

SSOP

(Top View)

P1[2]

(GPIO)P1[1]

(GPIO )

(GPIO) P1[7]

(GPIO) P2[2]

(GPIO ) P2[3]

(GPIO ) P2[4]

(GPIO ) P2[5]

(GPIO) 2[6]

(GPIO) P4[3]

(GPIO) P0[0]

( GPIO) P0[2]

( GPIO) P0[3]

( GPIO) P0[6]

(GPIO) P0[7]

XRES

VDDD

VSS

(GPIO )P1[0]

(GPIO)P3[1]

(GPIO )P3[2]

(GPIO )P3[3]

(GPIO)P2[7]

(GPIO)P4[2]

VCCD

(GPIO)P4[1]

(GPIO)P4[0]

C3 1µF

VSS

0.1 µF C2

C1 1µF

VSS

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