Family Datasheet

Document Number: 001-93576 Rev. *F

Page 8 of 37

Pinouts

The following is the pin-list for PSoC 4100. Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the optional

external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD

CapSense and Analog Mux Bus connections.

Notes:

1. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively.

2. P3.2 and P3.3 are SWD pins after boot (reset).

Descriptions of the pin functions are as follows:

VDDD

Pins

28-SSOP

Alternate Functions for Pins

Pin Description

Name

Type

Pin

Name

Analog

Alt 1

Alt 2

Alt 3

Alt 4

VSSD

Power

DN

–

–

–

–

–

–

Digital Ground

P2.2

GPIO

5

P2.2

sarmux.2

–

–

–

–

Port 2 Pin 2: gpio, lcd, csd, sarmux

P2.3

GPIO

6

P2.3

sarmux.3

–

–

–

–

Port 2 Pin 3: gpio, lcd, csd, sarmux

P2.4

GPIO

7

P2.4

sarmux.4

tcpwm0_p[1]

–

–

–

Port 2 Pin 4: gpio, lcd, csd, sarmux,

pwm

P2.5

GPIO

8

P2.5

sarmux.5

tcpwm0_n[1]

–

–

–

Port 2 Pin 5: gpio, lcd, csd, sarmux,

pwm

P2.6

GPIO

9

P2.6

sarmux.6

tcpwm1_p[1]

–

–

–

Port 2 Pin 6: gpio, lcd, csd, sarmux,

pwm

P2.7

GPIO

10

P2.7

sarmux.7

tcpwm1_n[1]

–

–

–

Port 2 Pin 7: gpio, lcd, csd, sarmux,

pwm

P3.0

GPIO

11

P3.0

–

tcpwm0_p[0]

scb1_uart_rx[0]

scb1_i2c_scl[0]

scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm,

scb1

P3.1

GPIO

12

P3.1

–

tcpwm0_n[0]

scb1_uart_tx[0]

scb1_i2c_sda[0]

scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm,

scb1

P3.2

GPIO

13

P3.2

–

tcpwm1_p[0]

–

swd_io

scb1_spi_clk[0]

Port 3 Pin 2: gpio, lcd, csd, pwm,

scb1, swd

P3.3

GPIO

14

P3.3

–

tcpwm1_n[0]

–

swd_clk

scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm,

scb1, swd

P4.0

GPIO

15

P4.0

–

–

scb0_uart_rx

scb0_i2c_scl

scb0_spi_mosi

Port 4 Pin 0: gpio, lcd, csd, scb0

P4.1

GPIO

16

P4.1

–

–

scb0_uart_tx

scb0_i2c_sda

scb0_spi_miso

Port 4 Pin 1: gpio, lcd, csd, scb0

P4.2

GPIO

17

P4.2

csd_c_mod

–

–

–

scb0_spi_clk

Port 4 Pin 2: gpio, lcd, csd, scb0

P4.3

GPIO

18

P4.3

csd_c_sh_tan

k

–

–

–

scb0_spi_ssel_0

Port 4 Pin 3: gpio, lcd, csd, scb0

P0.0

GPIO

19

P0.0

comp1_inp

–

–

–

scb0_spi_ssel_1

Port 0 Pin 0: gpio, lcd, csd, scb0,

comp

P0.1

GPIO

20

P0.1

comp1_inn

–

–

–

scb0_spi_ssel_2

Port 0 Pin 1: gpio, lcd, csd, scb0,

comp

P0.2

GPIO

21

P0.2

comp2_inp

–

–

–

scb0_spi_ssel_3

Port 0 Pin 2: gpio, lcd, csd, scb0,

comp

P0.3

GPIO

22

P0.3

comp2_inn

–

–

–

–

Port 0 Pin 3: gpio, lcd, csd, comp

P0.6

GPIO

23

P0.6

–

ext_clk

–

–

scb1_spi_clk[1]

Port 0 Pin 6: gpio, lcd, csd, scb1,

ext_clk

P0.7

GPIO

24

P0.7

–

–

–

wakeup

scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1,

wakeup

XRES

XRES

25

XRES

–

–

–

–

–

Chip reset, active low

VCCD

Power

26

VCCD

–

–

–

–

–

Regulated supply, connect to 1 µF

cap or 1.8 V

VDDD

Power

27

VDDD

–

–

–

–

–

Common power supply (Analog &

Digital) 1.8 V–5.5 V

VSSA

Power

28(DN)

VSS

–

–

–

–

–

Analog Ground

P1.0

GPIO

1

P1.0

ctb.oa0.inp

tcpwm2_p[1]

–

–

–

Port 1 Pin 0: gpio, lcd, csd, ctb, pwm

P1.1

GPIO

2

P1.1

ctb.oa0.inm

tcpwm2_n[1]

–

–

–

Port 1 Pin 1: gpio, lcd, csd, ctb, pwm

P1.2

GPIO

3

P1.2

ctb.oa0.out

tcpwm3_p[1]

–

–

–

Port 1 Pin 2: gpio, lcd, csd, ctb, pwm

P1.7

GPIO

4

P1.7

ctb.oa1.inp_a

lt ext_vref

––

–

–

Port 1 Pin 7: gpio, lcd, csd, ext_ref