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Automotive PSoC® 4: PSoC 4100

Family Datasheet

Document Number: 001-93576 Rev. *F

Page 7 of 37

GPIO

PSoC 4100 has 24 GPIOs. The GPIO block implements the

following:

■ Eight drive strength modes:

❐ Analog input mode (input and output buffers disabled)

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL).

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes.

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode and Hibernate modes).

■ Selectable slew rates for dV/dt related noise control to improve

EMI.

The pins are organized in logical entities called ports, which are

8-bit in width. During power-on and reset, the blocks are forced

to the disable state so as not to crowbar any inputs and/or cause

excess turn-on current. A multiplexing network known as a

high-speed I/O matrix is used to multiplex between various

signals that may connect to an I/O pin. Pin locations for

fixed-function peripherals are also fixed to reduce internal

multiplexing complexity.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it (5 for PSoC 4100).

Special Function Peripherals

LCD Segment Drive

The PSoC 4100 has an LCD controller which can drive up to four

commons and up to 32 segments. It uses full digital methods to

drive the LCD segments requiring no generation of internal LCD

voltages. The two methods used are referred to as digital

correlation and PWM.

Digital correlation pertains to modulating the frequency and

levels of the common and segment signals to generate the

highest RMS voltage across a segment to light it up or to keep

the RMS signal zero. This method is good for STN displays but

may result in reduced contrast with TN (cheaper) displays.

PWM pertains to driving the panel with PWM signals to

effectively use the capacitance of the panel to provide the

integration of the modulated pulse-width to generate the desired

LCD voltage. This method results in higher power consumption

but can result in better results when driving TN displays. LCD

operation is supported during Deep Sleep refreshing a small

display buffer (4 bits; 1 32-bit register per port).

CapSense

CapSense is supported on all pins in the PSoC 4100 through a

CapSense Sigma-Delta (CSD) block that can be connected to

any pin through an analog mux bus that any GPIO pin can be

connected to via an Analog switch. CapSense function can thus

be provided on any pin or group of pins in a system under

software control. A component is provided for the CapSense

block to make it easy for the user.

Shield voltage can be driven on another Mux Bus to provide

water tolerance capability. Water tolerance is provided by driving

the shield electrode in phase with the sense electrode to keep

the shield capacitance from attenuating the sensed input.

The CapSense block has two IDACs which can be used for

general purposes if CapSense is not being used.(both IDACs are

available in that case) or if CapSense is used without water

tolerance (one IDAC is available).

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