 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
HT85F2240 датащи(PDF) 17 Page - Holtek Semiconductor Inc |
|
|
|||||||||||||||||||||||||||||
HT85F2240 датащи(HTML) 17 Page - Holtek Semiconductor Inc |
|
|
17 / 147 page  Rev. 1.10 17 of 147 ���� �1� �01� A/D Flash 8051 Core Low Pin Count MCU HT85F2230/HT85F2240 6 Pin Descriptions With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. P0.0, P0.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name Function OPT I/T O/T Description P0.0/ICPDA/TDA P0.0 P0M0 P0M1 P0WAKE ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode and wake-�p. ICPDA — ICP Data Inp�t/O�tp�t TDA — Deb�g Data Inp�t/O�tp�t� on�� for EV chip P0.1/OSC1 P0.1 P0M0 P0M1 P0WAKE ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode and wake-�p. OSC1 HSOCR HXT — HXT pin P0.�/OSC� P0.� P0M0 P0M1 P0WAKE ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode and wake-�p. OSC� HSOCR — HXT HXT pin P0.�~P0.6 P0.�~P0.6 P0M0 P0M1 P0WAKE ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode and wake-�p. P0.7/[CC0] P0.7 P0M0 P0M1 P0WAKE ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode and wake-�p. CC0 PRM ST CMOS Compare/Capt�re inp�t/o�tp�t for PCA mod��e 0 P1.0/[CC1] P1.0 P1M0 P1M1 ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode CC1 PRM ST CMOS Compare/Capt�re inp�t/o�tp�t for PCA mod��e 1 P1.1 P1.1 P1M0 P1M1 ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode P1.�/AIN0 P1.� P1M0 P1M1 ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode AIN0 ADCR� AN — ADC Inp�t Channe� 0 P1.�/AIN6 P1.� P1M0 P1M1 ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode AIN6 ADCR� AN — ADC Inp�t Channe� 6 P1.4/AIN7 P1.4 P1M0 P1M1 ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode AIN7 ADCR� AN — ADC Inp�t Channe� 7 P�.0/CC0 P�.0 P�M0 P�M1 ST CMOS Genera� p�rpose I/O. Register se�ected I/O mode. CC0 PRM ST CMOS Compare/Capt�re inp�t/o�tp�t for PCA mod��e 0 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
