HT85F2240 datasheet(64/147 Pages) HOLTEK

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Rev. 1.10

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A/D Flash 8051 Core Low Pin Count MCU

HT85F2230/HT85F2240

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by an internal clock which is in turn supplied

by one of two sources selected by the WDTCS bit in the WDTCR register: a 32KHz clock or

fSYS/16. The 32KHz clock is sourced from the LIRC oscillator. The Watchdog Timer source clock

is then subdivided by a ratio of 16 to give a longer timeout. The LIRC internal oscillator has an

approximate period of 32KHz at a supply voltage of 5V. However, it should be noted that this

specified internal clock period can vary with VDD, temperature and process variations. The other

Watchdog Timer clock source option is the fSYS/16 clock.

Watchdog Timer Operation

The Watchdog Timer operates by providing a device reset when its 16-bit timer overflows. The

WDT is formed of two 8-bit registers, WDTL and WDTH, both of which are inaccessible to the

application program. The WDTH register of the Watchdog Timer is reloaded with the contents of

the WDTREL register. In the application program and during normal operation the user has to

strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from

executing a reset. This is done by setting the WDT and SWDT bits. If the program malfunctions

for whatever reason, jumps to an unknown location, or enters an endless loop, these clear-bit

instructions will not be executed in the correct manner as setup up by the user, in which case the

Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTCR

of “10101” to disable the WDT. A value of “01010” will enable the WDT while any other value will

execute an MCU reset. Using this methodology, enhanced device protection is provided. After

power on, these bits will have a value of “01010” which is the WDT enable setup value, and the

WDT function will be enabled and began counting. The application program can disable the WDT

at the beginning of the program if it is not required.

Watchdog Timer Enable/Disable Control

WE4 ~ WE0 Bits

WDT Function

01010B

Enab�e

10101B

Disab�e

Other va��es

Reset MCU

The watchdog timer must be refreshed regularly to prevent the reset request signal, WDTS,

from becoming active. This requirement imposes an obligation on the programmer to issue two

consecutive instructions. The first instruction is to set the WDT bit of the IEN0 register and the

second one is to set the SWDT bit in the IEN1 register. The maximum allowed delay time between

setting the WDT and SWDT bits is one instruction cycle, which means the instructions which set

the both bits should not be separated by any other instruction. If these instructions are not executed

consecutively then the WDT refresh procedure is incomplete and an unexpected WDT reset will

take place.

After the application program has set both the WDT and SWDT bits and the WDT refreshed, the

WDT bit as well the SWDT bit will be automatically cleared by hardware. The 8 high-order bits

of the Watchdog Timer are re-loaded with the contents of the WDTREL register. The larger the

WDTREL value, the shorter the WDT time out will be. For the maximum WDT time out value, the

WDTREL register should be cleared to zero.

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