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INA231AIYFDR датащи(PDF) 6 Page - Texas Instruments

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номер детали INA231AIYFDR
подробное описание детали  High- or Low-Side Measurement, Bidirectional Current and Power Monitor With 1.8-V I2C Interface
PDF  44 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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INA231AIYFDR датащи(HTML) 6 Page - Texas Instruments

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SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
t
(BUF)
S
S
P
P
6
INA231
SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017
www.ti.com
Product Folder Links: INA231
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
(1)
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are specified by design, but not
production tested.
7.6 Timing Requirements: I
2C Bus(1)
FAST MODE
HIGH-SPEED MODE
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
f(SCL) SCL operating frequency
0.001
0.4
0.001
2.5
MHz
t(BUF)
Bus free time between stop
and start conditions
600
260
ns
t(HDSTA)
Hold time after repeated
START condition.
After this period, the first clock
is generated.
100
100
ns
t(SUSTA)
Repeated start condition setup
time
100
100
ns
t(SUSTO) STOP condition setup time
100
100
ns
t(HDDAT) Data hold time, VS ≤ 3.3 V
0
0
130
ns
t(HDDAT) Data hold time, VS > 3.3 V
10
10
130
ns
t(SUDAT) Data setup time
100
50
ns
t(LOW) SCL clock low period
1300
260
ns
t(HIGH) SCL clock high period
600
60
ns
tF Data fall time
300
80
ns
tR Data rise time
300
80
ns
tF Clock fall time
300
40
ns
tR Clock rise time
300
40
ns
tR
Clock/data rise time for SCLK
≤ 100 kHz
1000
ns
Figure 1. Bus Timing Diagram



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