AD9671KBCZ datasheet(60/61 Pages) AD

60 / 61 page

Data Sheet

AD9671

Rev. A| Page 59 of 60

Addr.

(Hex)

Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

Comments

0x19C

JTX_

FRAME_

SIZE

Set frame

size

auto-

matically

0 =

disable

1 =

enable

(default)

0x10

Automatically

set JESD204B

frame size

(global).

0x19D

RESERVED_

19D

0x00

Reserved.

0x19E

RESERVED_

19E

0x10

Reserved.

Coefficient Registers

0x1000

0x1FFF

Coefficient

memory

256 × 112 bits

0x00

Global.

Profile Memory Registers

0xF00

0xFFF

Profile

memory

32 × 64 bits

0x00

Global.

MEMORY MAP REGISTER DESCRIPTIONS

For more information about the SPI memory map and other

functions, consult the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Update (Register 0x0FF)

All registers except Register 0x002 are updated as soon as they

are written. Writing to Register 0x0FF (the value written is don’t

care) initializes and updates the speed mode (Address 0x002)

and resets all other registers to their default values (analog and

ADC registers only; not the JESD204B registers, Register 0x000,

or Register 0x002). Set the speed mode in Register 0x002 and

write to Register 0x0FF at the beginning of the setup of the SPI

writes after the device is powered up to avoid rewriting other

registers after Register 0x0FF is written.

Profile Index and Software TX_TRIG (Register 0x10C)

The vector profile is selected using the profile index in

generates a TX_TRIG signal internal to the device. This signal

is asynchronous to the ADC sample clock. Therefore, do not

use this signal to align the data output, reset the digital

demodulator and decimator, or initiate advanced power mode

across multiple devices in the system. The external pin-driven

TX_TRIG± control is recommended for systems that require

synchronization of these features across multiple AD9671

devices.

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