AD9671KBCZ datasheet(44/61 Pages) AD

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Data Sheet

AD9671

Rev. A| Page 43 of 60

Table 28. Coefficient Memory for M = 4

Decimation Phase (j)

Index (i)

Table 29. Coefficient Block Mapping into SPI Memory Location

Coefficients (Eight Words × 14 Bits)

C7[13:0]

C6[13:0]

C5[13:0]

C4[13:0]

C3[13:0]

C2[13:0]

C1[13:0]

C0[13:0]

111:98

97:84

83:70

69:56

55:42

41:28

27:14

13:0

SPI Memory (14 Bytes)

B13[7:0]

B12[7:0]

B11[7:0]

B10[7:0]

B9[7:0]

B8[7:0]

B7[7:0]

B6[7:0]

B5[7:0]

B4[7:0]

B3[7:0]

B2[7:0]

B1[7:0]

B0[7:0]

111:104

103:96

95:88

87:80

79:72

71:64

63:56

55:48

47:40

39:32

31:24

23:16

15:8

7:0

DIGITAL TEST WAVEFORMS

Digital test waveforms can be used in the digital processing block

instead of the ADC output. To enable digital test waveforms,

use Address 0x11B. Enable each channel individually in

Address 0x11A.

Waveform Generator

For testing and debugging, use a programmable waveform

generator in place of ADC data. The waveform generator can

vary offset, amplitude, and frequency. The generator uses the ADC

sample frequency, fSAMPLE, and ADC full-scale amplitude, AFULL-SCALE,

as references. The values are set in Address 0x117, Address 0x118,

and Address 0x119 (see Table 33).

x = C + A × sin(2 × π × N)

(10)

SAMPLE 



, see Address 0x117

(11)

SCALE

FULL





, see Address 0x118

(12)

C = AFULL-SCALE × a × 2−(13 − b), see Address 0x119

(13)

Channel ID and Ramp Generator

In Channel ID test mode, the output is a concatenated value.

Bits[6:0] are a ramp. Bit 7 is 0 in real data mode or I channel

and 1 for Q channel in complex data mode. Bits[10:8] are the

channel ID such that Channel A is coded as 000 and Channel B

is 001. Bits[15:11] are the chip address.

Filter Coefficients

To check the filter coefficients, use a sequence of 1 followed by

0s for the input to the decimating FIR filter. The number of 0s is

the decimation rate times the number of taps (16). The output

shifter outputs the LSBs of the filter.

DIGITAL BLOCK POWER SAVING SCHEME

To reduce power consumption in the digital block, the

demodulator and decimation filter start in an idle state after

running the chip (Register 0x008, Bits[2:0] = 000). In the digital

idle state, the chip JESD204B block outputs zeroes and there is

no unnecessary digital processing of the ADC output data. The

digital block only switches to a running state when the negative

edge of the TX_TRIG± pulse is detected, or with a software

TX_TRIG± write (Register 0x10C, Bit 5 = 1).

To put the digital block back into the idle state (while the rest of

the chip is still running) and to save power, enact one of the

following three events: raise the TX_TRIG± signal high, write to

the profile index (Register 0x10C, Bits[0:4]), or allow the power

stop to expire by using the advanced power control feature.

Figure 59 illustrates the digital block power saving scheme.

CHIP IN POWER-DOWN,

STANDBY,

OR CW MODE

DIGITAL

DECIMATOR/FILTER

IDLE

DIGITAL

DECIMATOR/FILTER

RUNNING

RUN CHIP

NEGATIVE EDGE TX_TRIG±

OR S/W TX_TRIG±

TX_TRIG± IS HIGH, PROFILE

INDEX WRITE, OR POWER

STOP EXPIRES

Figure 59. Digital Block Power Saving Scheme

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