AD9671KBCZ datasheet(32/61 Pages) AD

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Data Sheet

AD9671

Rev. A| Page 31 of 60

JESD204B Synchronization Details

The AD9671 is a JESD204B Subclass 0 device and establishes

synchronization of the link through three control signals, TX_

TRIG, SYSREF, and SYNCINB, and typically a common device

clock. SYSREF, TX_TRIG, and SYNCINB are assumed to be

common to all converter devices for alignment purposes at the

system level.

The synchronization process is accomplished over three phases:

code group synchronization (CGS) phase, initial lane alignment

sequence (ILAS) phase, and data transmission phase. Note that

if scrambling is enabled, the bits are not actually scrambled until

the data transmission phase. The CGS and ILAS phases do not

use scrambling.

CGS Phase

In this phase, the JESD204B transmit block transmits /K28.5/

characters in response to a synchronization request from the

receiver (SYNCINB asserted). The receiver (external logic

device) must locate K28.5 characters in its input data stream

using clock and data recovery (CDR) techniques.

After a certain number of consecutive K28.5 characters are

detected on all link lanes, the receiver can optionally initiate a

SYS_REF edge so that the AD9671 transmit data establishes a

local multiframe clock (LMFC) internally. The AD9671 is a

Subclass 0 device that does not mandate SYS_REF for multi-

device synchronization. The use of SYS_REF reduces the latency

variation between devices and reduces the absolute latency of

each device to some extent. However, SYS_REF does not meet

the full requirements of a JESD204B Subclass 1 device, and the

primary synchronization tool on the AD9671 is to use the global

TX_TRIG signal to embed a START_CODE simultaneously into

the data stream for all devices.

After synchronizing all lanes, the receiver or logic device

deasserts the SYNCINB signal (SYNCINB± goes high), and the

transmitter block begins the ILAS phase, if enabled, on the next

internal LMFC boundary.

ILAS Phase

In the ILAS phase, the transmitter sends out a known pattern

and the receiver aligns all lanes of the link and verifies the

parameters of the link.

The ILAS phase begins after SYNCINB± is deasserted (goes

high). The transmit block begins to transmit four multiframes.

Dummy samples are inserted between the required characters

so that full multiframes are transmitted.

The four multiframes have the following properties:



Multiframe 1 begins with an /R/ character (K28.0) and

ends with an /A/ character (K28.3).



Multiframe 2 begins with an /R/ character, followed by a /Q/

(K28.4) character and link configuration parameters over

14 configuration octets (see Table 15), and ends with an

/A/ character. Many of the parameter values are of the

notation of the value − 1.



Multiframe 3 is the same as Multiframe 1.



Multiframe 4 is the same as Multiframe 1.

Data Transmission Phase

By the end of the ILAS phase, data transmission starts. Initiating a

global TX_TRIG signal resets any sampling edges within the

ADC and replaces a sample with the START_CODE (see

Address 0x18B and Address 0x18C in Table 33). Aligning the

data on all lanes based on the START_CODE guarantees the

synchronization across multiple lanes and across multiple devices.

In the data transmission phase, frame alignment is monitored

with control characters. Character replacement is used at the

end of frames. Character replacement in the transmitter occurs

in the following instances:



If scrambling is disabled and the last octet of the frame or

multiframe equals the octet value of the previous frame.



If scrambling is enabled and the last octet of the multiframe is

equal to 0x7C, or the last octet of a frame is equal to 0xFC.

Table 15. 14 Configuration Octets of the ILAS Phase

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

N’[4:0]

S[4:0]

CF[4:0]

Reserved, don’t care

FCHK[7:0]

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