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FDMF2011 датащи(PDF) 27 Page - ON Semiconductor |
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FDMF2011 датащи(HTML) 27 Page - ON Semiconductor |
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27 / 31 page ![]() © 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF2011 Rev.1.0 26 However, similar operation can arise when a switching converter (such as a synchronous buck) is pulling energy from the output filter capacitors and delivering the energy back to the input filter capacitors. Figure 67. Synchronous Boost Converter operating in CCM From a module perspective, the main difference here versus the previous (buck) operating mode is that this situation will cause the LS FET (Q2) to act as the control MOSFET and hard switch while the HS FET (Q1) acts as a synchronous rectifier and undergoes soft switching with body diode recovery. This type of operation can drastically change power losses dissipated in Q1 and Q2 versus buck operating mode. dVDS/dt control using external gate resistors The FDMF2011 also provides module pins for placing external gate resistors. The module provides pins for the HO and LO signals (driver output signals) and the HG and LG (Power MOSFET gate pins). Resistors can be placed in series with the MOSFET gate to control the SW node edge rates. Independently controlling MOSFET (slower) turn-on and (faster) turn-off slew rates can also be accomplished by using the resistor and diode circuit shown in Figure 68.. Figure 68. Gate drive resistor-diode circuit CGD x dVDS/dt turn-on CGD x dVDS/dt turn-on is a false (unwanted) turn-on event that often creates a brief and uncontrolled shoot through current between the HS (Q1) and LS (Q2) MOSFETs. Typically, a CGD x dVDS/dt “shoot-through” condition arises from capacitive feedback current flowing through CGD into CGS inducing a gate-bounce-induced channel turn-on of the MOSFET. Holding the gate below threshold can become challenging because the high- frequency capacitive displacement current from CGD (due to dVDS/dt) couples back to circuit ground through the gate electrode. Figure 69. CGD x dVDS/dt current flow Ld_LS Ls_LS LG_brd LG_pack RG RDRIVE_LS Q2 CGD CGS ZGate_Drv ~ R + ωL ZMOS_Gate ~ 1/ωC |
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