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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FDMF2011 датащи(PDF) 24 Page - ON Semiconductor |
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FDMF2011 датащи(HTML) 24 Page - ON Semiconductor |
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24 / 31 page  © 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF2011 Rev.1.0 23 Driver Output Stage The driver IC output stage is designed to drive a pair of N-channel MOSFETs. The driver outputs (LO, HO) are non-inverting and will follow the PWM input commands (LI, HI respectively). The LO and HO outputs are capable of sinking and sourcing up to 0.65/0.35A peak current respectively. The driver output stage is also capable of providing a rail (VDD) to rail (VSS) output voltage level when driving the Power MOSFETs. Depending on the end application, the output voltage level can be set to aide in optimizing MOSFET and driver IC power losses. The driver output voltage level can also be used to help adjust SW node edge rates. Timing Diagram Figure 64. PWM Timing Diagram (LI / HI signals) |
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