OX16CF950 datasheet(38/60 Pages) ETC

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Page 38

OXCF950 DATA SHEET V1.1

OXFORD SEMICONDUCTOR LTD.

= Sample clock values defined in TCR[3:0]

Divisor = DLL + ( 256 x DLM )

Prescaler= 1 when MCR[7] = ‘0’ else:

= M + ( N / 8 ) where:

= CPR[7:3] (Integer part – 1 to 31)

= CPR[2:0] (Fractional part – 0.000 to 0.875 )

See next section for a discussion of the clock prescaler and

times clock register.

After a hardware reset, the prescaler is bypassed (set to 1)

and TCR is set to 0x00 (i.e. SC = 16). Assuming this

default configuration, the following table gives the divisors

required to be programmed into the DLL and DLM registers

in order to obtain various standard baud rates:

DLM:DLL

Divisor Word

Baud Rate

(bits per second)

0x0900

0x0300

110

0x0180

300

0x00C0

600

0x0060

1,200

0x0030

2,400

0x0018

4,800

0x000C

9,600

0x0006

19,200

0x0004

28,800

0x0003

38,400

0x0002

57,600

0x0001

115,200

Table 32: Standard PC COM Port Baud Rate Divisors

(assuming a 1.8432MHz crystal)

6.10.2 Clock Prescaler Register ‘CPR’

The CPR register is located at offset 0x01 of the ICR

The prescaler divides the system clock by any value in the

range of 1 to “31 7/8” in steps of 1/8. The divisor takes the

form “M + N/8”, where M is the 5 bit value defined in

CPR[7:3] and N is the 3 bit value defined in CPR[2:0].

The prescaler is by-passed and a prescaler value of ‘1’ is

selected by default when MCR[7] = 0.

MCR[7] is reset to ‘0’ after a hardware reset but may be

overwritten by software. Note however that since access to

MCR[7] is restricted to Enhanced mode only, EFR[4]

should first be set and then MCR[7] set or cleared as

required.

If MCR[7] is set by software, the internal clock prescaler is

enabled.

Upon a hardware reset, CPR defaults to 0x20 (division-by-

4). Compatibility with existing 16C550 baud rate divisors is

maintained using a 1.8432MHz clock.

For higher baud rates use a higher frequency clock, e.g.

14.7456MHz, 18.432MHz, 32MHz, 40MHz or 60.0MHz.

The flexible prescaler allows system designers to generate

popular baud rates using clocks that are not integer

multiples of the required rate. When using a non-standard

clock frequency, compatibility with existing 16C550

software drivers may be maintained with a minor software

patch to program the on-board prescaler to divide the high

frequency clock down to 1.8432MHz.

Table 34 on the following page gives the prescaler values

required to operate the UARTs at compatible baud rates

with various different crystal frequencies. Also given is the

maximum available baud rates in TCR = 16 and TCR = 4

modes with CPR = 1.

6.10.3 Times Clock Register ‘TCR’

The TCR register is located at offset 0x02 of the ICR

The 16C550 and other compatible devices such as 16C650

and 16C750 use a 16 times (16x) over-sampling channel

clock. The 16x over-sampling clock means that the channel

clock runs at 16 times the selected serial bit rate. It limits

the highest baud rate to 1/16 of the system clock when

using a divisor latch value of unity. However, the 950

UART is designed in a manner to enable it to accept other

multiplications of the bit rate clock. It can use values from

4x to 16x clock as programmed in the TCR as long as the

clock (oscillator) frequency error, stability and jitter are

within reasonable parameters. Upon hardware reset the

TCR is reset to 0x00 which means that a 16x clock will be

used, for compatibility with the 16C550 and compatibles.

The maximum baud-rates available for various system

clock frequencies at all of the allowable values of TCR are

indicated in Table 35 on the following page. These are the

values in bits-per-second (bps) that are obtained if the

divisor latch = 0x01 and the Prescaler is set to 1.

The OXCF950 has the facility to operate at baud-rates up

to 15 Mbps at 5V.

The table below indicates how the value in the register

corresponds to the number of clock cycles per bit. TCR[3:0]

is used to program the clock. TCR[7:4] are unused and will

return “0000” if read.

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