AD7664ASTZ datasheet(18/25 Pages) AD

18 / 25 page

REV.

AD7664

–17–

Because the AD7664 is used with a fast throughput, the Mas-

ter Read During Conversion Mode is the most often recom-

mended Serial Mode, when it can be used. In this mode, the

serial clock and data toggle at appropriate instants that mini-

mize potential feedthrough between digital activity and the

critical conversion decisions.

In Read-after-Conversion Mode, it should be noted that, unlike

in other modes, the signal BUSY returns LOW after the 16 data

bits are pulsed out and not at the end of the conversion phase,

which results in a longer BUSY width.

SLAVE SERIAL INTERFACE

External Clock

The AD7664 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/

INT pin is

held HIGH. In this mode, several methods can be used to read

the data. The external serial clock is gated by

CS. When CS and

RD are both LOW, the data can be read after each conversion

or during the following conversion. The external clock can be

either a continuous or discontinuous clock. A discontinuous

clock can be either normally HIGH or normally LOW, when

inactive. Figures 18 and 20 show the detailed timing diagrams of

these methods.

While the AD7664 is performing a bit decision, it is important

that voltage transients not occur on digital input/output pins or

degradation of the conversion result could occur. This is par-

ticularly important during the second half of the conversion

phase, because the AD7664 provides error correction circuitry

that can correct for an improper bit decision made during the

first half of the conversion phase. For this reason, it is recom-

mended that when an external clock is being provided, it is a

discontinuous clock that is toggling only when BUSY is LOW

or, more importantly, that it does not transition during the latter

half of BUSY HIGH.

External Discontinuous Clock Data Read after Conversion

Though the maximum throughput cannot be achieved using this

mode, it is the most often recommended of the serial Slave

Modes. Figure 18 shows the detailed timing diagrams of this

method. After a conversion is complete, indicated by BUSY

returning LOW, the result of this conversion can be read

while both

CS and RD are LOW. The data is shifted out,

MSB first, with 16 clock pulses and is valid on both the rising

and falling edge of the clock.

Among the advantages of this method, the conversion perfor-

mance is not degraded, because there are no voltage tran-

sients on the digital interface during the conversion process.

Another advantage is the ability to read the data at any speed up to

40 MHz, which accommodates both slow digital host interface

and the fastest serial reading.

Finally, in this mode only, the AD7664 provides a daisy-chain

feature using the RDC/SDIN input pin for cascading multiple

converters together. This feature is useful for reducing component

count and wiring connections when desired as, for instance, in

isolated multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 19. Simultaneous sampling is possible by using a com-

mon

CNVST signal. It should be noted that the RDC/SDIN

input is latched on the edge of SCLK opposite to the one used

to shift out the data on SDOUT. Therefore, the MSB of the

upstream converter just follows the LSB of the downstream

converter on the next SCLK cycle.

CNVST

SCLK

SDOUT

RDC/SDIN

BUSY

DATA

OUT

AD7664

(DOWNSTREAM)

BUSY

OUT

CNVST

SCLK

AD7664

(UPSTREAM)

RDC/SDIN

SDOUT

SCLK IN

CS IN

CNVST IN

Figure 19. Two AD7664s in a Daisy-Chain Configuration

SCLK

SDOUT

D15

D14

D13

X15

X14

X13

Y15

Y14

BUSY

SDIN

EXT/

INT = 1

INVSCLK = 0

t35

t36 t37

t31

t32

t16

t33

X15

X14

1617

RD = 0

t34

Figure 18. Slave Serial Data Timing for Reading (Read after Convert)

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