REV.

F

AD7664

–5–

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Type

Description

1

AGND

P

Analog Power Ground Pin.

2

AVDD

P

Input Analog Power Pins. Nominally 5 V.

3, 40–42,

NC

No Connect.

44–48

4

DGND

DI

Must Be Tied to the Ground Where DVDD Is Referred.

5OB/

2C

DI

Straight Binary/Binary Twos Complement. When OB/

2C is HIGH, the digital output is

straight binary; when LOW, the MSB is inverted resulting in a twos complement output from

its internal shift register.

6

WARP

DI

Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the

maximum throughput is achievable, and a minimum conversion rate must be applied in order

to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of

the minimum conversion rate.

7

IMPULSE

DI

Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In

this mode, the power dissipation is approximately proportional to the sampling rate.

8

SER/

PAR

DI

Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the

Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.

9–12

D[0:3]

DO

Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless

of the state of SER/

PAR.

13

D4

DI/O

When SER/

PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.

or EXT/

INT

When SER/

PAR is HIGH, this input, part of the Serial Port, is used as a digital select input

for choosing the internal or an external data clock. With EXT/

INT tied LOW, the internal

clock is selected on the SCLK output. With EXT/

INT set to a logic HIGH, output data is

synchronized to an external clock signal connected to the SCLK input.

14

D5

DI/O

When SER/

PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.

or INVSYNC

When SER/

PAR is HIGH, this input, part of the Serial Port, is used to select the active state

of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active

HIGH. When HIGH, SYNC is active LOW.

15

D6

DI/O

When SER/

PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.

or INVSCLK

When SER/

PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.

It is active in both Master and Slave Mode.

PIN CONFIGURATION

AGND

AVDD

NC

DGND

OB/2C

WARP

IMPULSE

SER/PAR

D0

D1

D2

D3

AGND

CNVST

PD

RESET

CS

RD

DGND

BUSY

D15

D14

D13

D12

AD7664

TOP VIEW

(Not to Scale)

25

26

27

28

29

30

31

32

33

34

35

36

1

2

3

4

5

6

7

8

9

10

11

12

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EPAD IS CONNECTED TO GROUND; HOWEVER,

THIS CONNECTION IS NOT REQUIRED TO MEET

SPECIFIED PERFORMANCE.