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AD7992 датащи(PDF) 17 Page - Analog Devices |
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AD7992 датащи(HTML) 17 Page - Analog Devices |
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17 / 29 page ![]() AD7992 Rev. 0 | Page 16 of 28 INTERNAL REGISTER STRUCTURE The AD7992 contains 11 internal registers (see Figure 24) that are used to store conversion results, high and low conversion limits, and information to configure and control the device. There are ten data registers and one address pointer register. CONVERSION RESULT REGISTER ALERT STATUS REGISTER CYCLE TIMER REGISTER HYSTERESIS REGISTER CH1 HYSTERESIS REGISTER CH2 CONFIGURATION REGISTER DATALOW REGISTER CH1 DATALOW REGISTER CH2 DATAHIGH REGISTER CH2 DATAHIGH REGISTER CH1 ADDRESS POINTER REGISTER SERIAL BUS INTERFACE SDA SCL D A T A Figure 24. AD7992 Register Structure Each data register has an address that the address pointer register points to when communicating with it. The conversion result register is the only data register that is read-only. ADDRESS POINTER REGISTER Because it is the register to which the first data byte of every write operation is written automatically, the address pointer register does not have and does not require an address. The address pointer register is an 8-bit register in which the 4 LSBs are used as pointer bits to store an address that points to one of the AD7992’s data registers. The 4 MSBs are used as command bits when operating in Mode 2 (see the Modes of Operation section). The first byte following each write address is the address of one of the data registers, which is stored in the address pointer register and selects the data register to which subsequent data bytes are written. Only the 4 LSBs of this register are used to select a data register. On power-up, the address pointer register contains all 0s, pointing to the conversion result register. Table 7. Address Pointer Register C4 C3 C2 C1 P3 P2 P1 P0 0 0 0 0 Register select Table 8. AD7992 Register Addresses P3 P2 P1 P0 Registers 0 0 0 0 Conversion result register (read) 0 0 0 1 Alert status register (read/write) 0 0 1 0 Configuration register (read/write) 0 0 1 1 Cycle Timer register (read/write) 0 1 0 0 DATALOW register CH1 (read/write) 0 1 0 1 DATAHIGH register CH1 (read/write) 0 1 1 0 Hysteresis register CH1 (read/write) 0 1 1 1 DATALOW register CH2 (read/write) 1 0 0 0 DATAHIGH register CH2 (read/write) 1 0 0 1 Hysteresis register CH2 (read/write) |
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