SOLOMON

Rev 1

01/2003

SSD1801 Series

12

FUNCTIONAL BLOCK DESCRIPTIONS

Command Decoder and Command Interface

This module determines whether the input data is interpreted as data or command. Data is directed to this module

based upon the input of the D/ C pin. If D/ C is high, data is written to internal memories (DDRAM, CGRAM,

the corresponding command register.

MPU Parallel 6800-series Interface in 8 bits bus mode

input high indicates a read operation from the internal RAM (DDRAM, CGRAM and ICONRAM). R/W( WR ) input low

indicates a write operation to internal RAM (DDRAM, CGRAM and ICONRAM) or Internal Command Registers

depending on the status of D/ C input. The E( RD ) input serves as data latch signal (clock) when high provided that

CS are low. Refer to Figure 20 for Parallel Interface Timing Diagram of 6800-series microprocessors.

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline

processings are internally performed which require the insertion of a dummy read before the first actual display data

read. This is shown in Figure 4 below. The dummy read make the address counter (AC) increased by 1. So it is

recommended to set address again before writing. The consecutive read after the dummy read are also the valid

data. The instruction read cycle is not supported and it is regarded as a no operation cycle.

MPU Parallel 8080-series Interface in 8 bits bus mode

serves as data read latch signal (clock) when low provided that CS is low whether it is Command write or internal

RAM read/ write is controlled by D/ C. R/W( WR ) input serves as data write latch signal (clock) when low provided

that CS is low. Refer to Figure 21 for Parallel Interface Timing Diagram of 8080-series microprocessor.

Similar to 6800-series interface, a dummy read is also required before the first actual display data read.

4-bit MPU Parallel 6800/8080-Series Interface

The control of 4-bit bus mode is exactly the same as 8-bit bus mode except 2 consecutive access (read/ write) is

needed to read/ write 8 bits data. For write operation, upper order bits are written before the low order bits, and low

order bits are always read before the upper order bit in read transaction.

MPU Serial Interface

determine whether the data byte in the shift register is written to the internal RAM (DDRAM, CGRAM, ICONRAM) or

command register at the same clock.

Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry. The oscillator generates the clock for the DC-DC

voltage converter. This clock is also used in the Display Timing Generator.

ADDRESS COUNTER (AC)

Address Counter (AC) in SSD1801 stores DDRAM/ CGRAM/ ICONRAM address. After writing into or reading

from DDRAM/ CGRAM/ ICONRAM. AC is automatically increased by 1. There is only one address counter and stores

the address among DDRAM / CGRAM / ICONRAM.