SOLOMON

Rev 1

01/2003

SSD1801 Series

20

Software control of 1/4 and 1/5 bias ratio to match the characteristic of LCD panel.

Reset Circuit

This block includes Power On Reset circuitry and the Reset pin RES . Both of these having the same reset

function. Once RES receives a negative reset pulse, all internal circuitry will start to initialize. Minimum pulse width

for completing the reset sequence is 10ms.

The status of the chip after reset is given by:

1. Display/ cursor/ blink is turned OFF

2. 2-line display mode

3. Power control register is set to 000b

4. Oscillator is OFF

5. Power save is OFF

6. CGRAM is not used

7. Shift register data clear in serial interface

8. Bias ratio is set to 1/5

9. Address counter is set to 00h

10. Normal scan direction of the COM outputs

11. Contrast control register is set to 00h

12. Test mode is turned OFF

13. In case of 4-bit interface mode selection, SSD1801 considers the 1st 4-bit data from MPU as the

high order bits.

14. The 1st line of display is the address 00h-0Fh.

Display Data Latch

A series of registers carrying the display signal information. For SSD1801, there are 105 latches (80 + 25) for

holding the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage levels.

Level Selector

Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and

used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV

Buffer Cell, which in turn outputs the COM or SEG LCD waveform.

HV Buffer Cell (Level Shifter)

Buffer Cell work as a level shifter which translates the low voltage output signal to the required driving voltage.

The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage

levels are given by the level selector which is synchronized with the internal M signal.