AD9874ABST datasheet(21/41 Pages) AD

21 / 41 page

REV. A

AD9874

–20–

An example may help illustrate how the values of LOA, LOB,

and LOR can be selected. Consider an application employing

a 13 MHz crystal oscillator (i.e., fREF = 13 MHz) with the

requirement that fREF = 100 kHz and fLO = 143 MHz (i.e.,

high side injection with fIF = 140.75 MHz and fCLK = 18 MSPS).

LOR is selected to be 130 such that fREF = 100 kHz. The

N-divider factor is 1430, which can be realized by selecting

LOB = 178 and LOA = 6.

The stability, phase noise, spur performance, and transient

response of the AD9874’s LO (and CLK) synthesizers are

determined by the external loop filter, the VCO, the N-divide

factor, and the reference frequency, FREF. A good overview

of the theory and practical implementation of PLL synthesiz-

ers (featured as a three-part series in Analog Dialogue) can

be found at:

• www.analog.com/library/analogDialogue/archives/33-03/

phase/index.html

• www.analog.com/library/analogDialogue/archives/33-05/

phase_locked/index.html

• www.analog.com/library/analogDialogue/archives/33-07/

phase3/index.html

Also, a free software copy of the Analog Devices ADIsimPLL,

a PLL synthesizer simulation tool, is available at www.analog.com.

Note that the ADF4112 model can be used as a close approxima-

tion to the AD9874’s LO synthesizer when using this software tool.

FREF

84k

~VDDL/2

BUFFER

500

TO MIXER

LO PORT

1.75V

BIAS

LOP

LON

NOTES

1. ESD DIODE STRUCTURES OMITTED FOR CLARITY.

2. FREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON.

Figure 6. Equivalent Input of LO and REF Buffers

Figure 6 shows the equivalent input structures of the synthesiz-

ers’ LO and REF buffers (excluding the ESD structures).

The LO input is fed to the LO synthesizer’s buffer as well as

the AD9874’s mixer’s LO port. Both inputs are self-biasing

and thus tolerate ac-coupled inputs. The LO input can be

driven with a single-ended or differential signal. Single-ended

dc-coupled inputs should ensure sufficient signal swing above

and below the common-mode bias of the LO and REF buffers

(i.e., 1.75 V and VDDL/2). Note that the fREF input is slew rate

dependent and must be driven with input signals exceeding

7.5 V/ s to ensure proper synthesizer operation. If this con-

dition can not be met, an external logic gate can be inserted

prior to the fREF input to “square-up” the signal thus allowing a

fREF input frequency approching dc.

Fast Acquire Mode

The fast acquire circuit attempts to boost the output current

when the phase difference between the divided-down LO

(i.e., fLO) and the divided-down reference frequency (i.e., fREF)

exceeds the threshold determined by the LOFA register. The

LOFA register specifies a divisor for the fREF signal that deter-

mines the period (T) of this divided-down clock. This period

defines the time interval used in the fast acquire algorithm to

control the charge pump current.

Assume for the moment that the nominal charge pump current

is at its lowest setting (i.e., LOI = 0) and denote this minimum

current by I0. When the output pulse from the phase compara-

tor exceeds T, the output current for the next pulse is 2I0.

When the pulse is wider than 2T, the output current for the

next pulse is 3I0, and so forth, up to eight times the minimum

output current. If the nominal charge pump current is more

than the minimum value (i.e., LOI > 0), the preceding rule is

only applied if it results in an increase in the instantaneous

charge pump current. If the charge pump current is set to its

lowest value (LOI = 0) and the fast acquire circuit is enabled,

the instantaneous charge pump current will never fall below 2I0

when the pulsewidth is less than T. Thus, the charge pump

current when fast acquire is enabled is given by:

LOI Pulsewidth T

PUMP FA

−

=× +

{

max( ,

)}

(4)

The recommended setting for LOFA is LOR/16. Choosing a

larger value for LOFA will increase T. Thus, for a given phase

difference between the LO input and the fREF input, the instan-

taneous charge pump current will be less than that available for

a LOFA value of LOR/16. Similarly, a smaller value for LOFA

will decrease T, making more current available for the same

phase difference. In other words, a smaller value of LOFA will

enable the synthesizer to settle faster in response to a frequency

hop than will a large LOFA value. Care must be taken to choose

a value for LOFA that is large enough (values greater than 4

recommended) to prevent the loop from oscillating back and

forth in response to a frequency hop.

Table VII. SPI Registers Associated with LO Synthesizer

Address

Bit

Default

(Hex)

Breakdown

Width

Value

Name

0x00

(7:0)

0xFF

STBY

0x08

(5:0)

0x00

LOR(13:8)

0x09

(7:0)

0x38

LOR(7:0)

0x0A

(7:5)

0x5

LOA

(4:0)

0x00

LOB(12:8)

0x0B

(7:0)

0x1D

LOB(7:0)

0x0C

(6)

LOF

(5)

LOINV

(4:2)

LOI

(1:0)

LOTM

0x0D

(3:0)

0x0

LOFA(13:8)

0x0E

(7:0)

0x04

LOFA(7:0)

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