AD9874ABST datasheet(16/41 Pages) AD

16 / 41 page

REV. A

AD9874

–15–

SERIAL PORT INTERFACE (SPI)

The serial port of the AD9874 has 3-wire or 4-wire SPI capability,

allowing read/write access to all registers that configure the

device’s internal parameters. The default 3-wire serial commu-

nication port consists of a clock (PC), peripheral enable (PE), and

bidirectional data (PD) signal. The inputs to PC, PE, and PD

contain a Schmitt trigger with a nominal hysteresis of 0.4 V

centered about the digital interface supply (i.e., VDDH/2).

A 4-wire SPI interface can be enabled by setting the MSB of the

SSICRB register (Reg. 0x19, Bit 7), resulting in the output data

also appearing on the DOUTB pin. Note that since the default

power-up state sets DOUTB low, bus contention is possible for

systems sharing the SPI output line. To avoid any bus contention,

the DOUTB pin can be three-stated by setting the fourth control

bit in the three-state bit (Reg 0x3B, Bit 3). This bit can then be

toggled to gain access to the shared SPI output line.

An 8-bit instruction header must accompany each read and

write SPI operation. Only the write operation supports an auto-

increment mode, allowing the entire chip to be configured in a

single write operation. The instruction header is shown in

Table II. It includes a read/not-write indicator bit, six address

bits, and a don’t care bit. The data bits immediately follow the

instruction header for both read and write operations. Note that

the address and data are always given MSB first.

Table II. Instruction Header Information

MSB

LSB

R/W

Figure 1a illustrates the timing requirements for a write opera-

tion to the SPI port. After the peripheral enable (PE) signal goes

low, data (PD) pertaining to the instruction header is read on

the rising edges of the clock (PC). To initiate a write operation,

the read/not-write bit is set low. After the instruction header is

read, the eight data bits pertaining to the specified register are

shifted into the data pin (PD) on the rising edge of the next

eight clock cycles. PE stays low during the operation and goes

high at the end of the transfer. If PE rises before the eight clock

cycles have passed, the operation is aborted.

If PE stays low for an additional eight clock cycles, the destina-

tion address is incremented and another eight bits of data are

shifted in. Again, should PE rise early, the current byte is

ignored. By using this implicit addressing mode, the entire

chip can be configured with a single write operation. Regis-

ters identified as being subject to frequent updates, namely

those associated with power control and AGC operation, have

been assigned adjacent addresses to minimize the time required

to update them. Note that multibyte registers are big-endian

(the most significant byte has the lower address) and are updated

when a write to the least significant byte occurs.

Figure 1b illustrates the timing for a read operation to the SPI

port. Although the AD9874 does not require read access for

proper operation, it is often useful in the product development

phase or for system authentication. Note that the readback

enable bit (Register 0x3A, Bit 3) must be set for a read opera-

tion with a 3-wire SPI interface. After the peripheral enable

(PE) signal goes low, data (PD) pertaining to the instruction

header is read on the rising edges of the clock (PC). A read

operation occurs if the read/not-write indicator is set high. After

the address bits of the instruction header are read, the eight data

bits pertaining to the specified register are shifted out of the

data pin (PD) on the falling edges of the next eight clock cycles.

If the 4-wire SPI interface is enabled, the eight data bits will

also appear on the DOUTB pin with the same timing relation-

ship as those appearing at PD. After the last data bit is shifted

out, the user should return PE high, causing PD to become

three-stated and return to its normal status as an input pin.

Since the auto increment mode is not supported for read opera-

tions, an instruction header is required for each register read

operation and PE must return high before initiating the next

read operation.

DON’T

CARE

R/W

tCLK

tHI

tLOW

tEZ

tDS

tDH

tDV

DOUTB

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

Figure 1b. SPI Read Operation Timing

DON’T

CARE

R/W

tDS

tDH

tCLK

tHI

tLOW

Figure 1a. SPI Write Operation Timing

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