AD6677EBZ datasheet(28/48 Pages) AD

28 / 48 page

AD6677

Data Sheet

Rev. C | Page 28 of 48

Table 12. JESD204B Configuration Table Used in ILAS and

CHKSUM Calculation

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

Subclass[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Set Additional Digital Output Configuration Options

Other data format controls include the following:



Invert polarity of serial output data, Address 0x60, Bit 1



ADC data format select (offset binary or twos complement),

Address 0x14, Bits[1:0]



Options for interpreting signal on SYNCINB± and SYSREF±,

Address 0x3A, Bits[4:0]

Reenable Lane After Configuration

After modifying the JESD204B link parameters, enable the link

so that the synchronization process can begin. This is accomplished

by writing Logic 0 to Address 0x5F, Bit 0.

CONVERTER

INPUT

SYSREF±

SYNCINB±

CONVERTER

SAMPLE

AD6677 IF RECEIVER

SERDOUT0±

JESD204B LANE CONTROL

(M = 1, L = 1)

Figure 51. Transmit Link Simplified Block Diagram

8B/10B

ENCODER/

CHARACTER

REPLACEMENT

SERIALIZER

~SYNC

SYSREF

VINA+

(MSB)

(LSB)

VINA–

SERDOUT±

A PATH

ADC

TEST PATTERN

16-BIT

JESD204B

TEST PATTERN

8-BIT

ADC

A10

S10

S11

S12

S13

S14

S15

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

OPTIONAL

SCRAMBLER

1 + x14 + x15

JESD204B

TEST PATTERN

10-BIT

Figure 52. Digital Processing of JESD204B Lane The Octet 0/1

Table 13. JESD204B Typical Configurations

JESD204B

Configure

Setting

M (No. of Converters),

Address 0x71,

Bits[7:0]

L (No. of Lanes),

Address 0x6E,

Bits[4:0]

F (Octets/Frame),

Address 0x6F,

Bits[7:0], Read Only

S (Samples/ADC/Frame),

Address 0x74, Bits[4:0],

Read Only

HD (High Density Mode),

Address 0x75, Bit 7,

Read Only

0x11 (Default)

DATA

FROM

ADC

FRAME

ASSEMBLER

(ADD TAIL BITS)

OPTIONAL

SCRAMBLER

1 + x14 + x15

8B/10B

ENCODER

RECEIVER

Figure 53. ADC Output Data Path

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