AD6677EBZ datasheet(25/48 Pages) AD

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Data Sheet

AD6677

Rev. C | Page 25 of 48

DIGITAL OUTPUTS

JESD204B TRANSMIT TOP LEVEL DESCRIPTION

The AD6677 digital output uses the JEDEC Standard No.

JESD204B, Serial Interface for Data Converters. JESD204B is a

protocol to link the AD6677 to a digital processing device over a

serial interface of up to 5 Gbps link speeds. The benefits of the

JESD204B interface include a reduction in required board area

for data interface routing and the enabling of smaller packages

for converter and logic devices. The AD6677 supports single or

dual lane interfaces.

JESD204B Overview

The JESD204B data transmit block assembles the parallel data from

the ADC into frames and uses 8B/10B encoding as well as optional

scrambling to form serial output data. Lane synchronization is

supported using special characters during the initial establishment

of the link and additional synchronization is embedded in the

data stream thereafter. A matching external receiver is required

to lock onto the serial data stream and recover the data and clock.

For additional details on the JESD204B interface, refer to the

JESD204B standard.

The AD6677 JESD204B transmit block maps the output of the

ADC over a single link. The link is configured to use a single

pair of serial differential outputs that is called a lane. The

JESD204B specification refers to a number of parameters to

define the link, and these parameters must match between the

JESD204B transmitter (AD6677 output) and receiver.

The JESD204B link is described according to the following

parameters:

•

S = samples transmitted per single converter per frame

cycle (AD6677 value = 1)

•

M = number of converters per converter device

(AD6677 value = 1)

•

L = number of lanes per converter device (AD6677 value = 1)

•

N = converter resolution (AD6677 value = 11)

•

N’ = total number of bits per sample (AD6677 value = 16)

•

CF = number of control words per frame clock cycle per

converter device (AD6677 value = 0)

•

CS = number of control bits per conversion sample

(configurable on the AD6677 up to 2 bits)

•

K = number of frames per multiframe (configurable on

the AD6677)

•

HD = high density mode (AD6677 value = 0)

•

F = octets/frame (AD6677 value = 2)

•

C = control bit (overrange, overflow, underflow; available

on the AD6677)

•

T = tail bit (available on the AD6677)

•

SCR = scrambler enable/disable (configurable on the AD6677)

•

FCHK = checksum for the JESD204B parameters

(automatically calculated and stored in register map)

Figure 51 shows a simplified block diagram of the AD6677

JESD204B link. The AD6677 is configured to use one converter

and one lane. Converter data is output to SERDOUT0+/

SERDOUT0−. The AD6677 allows for other configurations such

as combining the outputs of both converters onto a single lane or

changing the mapping of the A and B digital output paths. These

modes are set up through a quick configuration register in the

By default, in the AD6677, the 11-bit converter word is divided

into two octets (8 bits of data). Bit 10 (MSB) through Bit 3 are in

the first octet. The second octet contains Bit 2 through Bit 0 (LSB),

followed by three bits that can be programmed as 0 or pseudo-

random numbers with two tail bits added to fill the second

octet. The tail bits can be configured as zeros, a pseudo-random

number sequence, or control bits indicating overrange,

underrange, or valid data conditions.

The two resulting octets can be scrambled. Scrambling is

optional, however, it is available to avoid spectral peaks when

transmitting similar digital data patterns. The scrambler uses a

self synchronizing, polynomial-based algorithm defined by the

1 + x14 + x15 equation. The descrambler in the receiver must be a

self synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8B/10B encoder. The

8B/10B encoder works by taking eight bits of data (an octet) and

encoding them into a 10-bit symbol. Figure 52 shows how the

11-bit data is taken from the ADC, the tail bits are added, the two

octets are scrambled, and how the octets are encoded into two

10-bit symbols. Figure 52 illustrates the default data format.

At the data link layer, in addition to the 8B/10B encoding, the

character replacement allows the receiver to monitor frame

alignment. The character replacement process occurs on the frame

and multiframe boundaries. Implementation depends on which

boundary is occurring and if scrambling is enabled.

If scrambling is disabled, the following applies:

•

If the last scrambled octet of the last frame of the multiframe

equals the last octet of the previous frame, the transmitter

replaces the last octet with the control character /A/ = /K28.3/.

•

On other frames within the multiframe, if the last octet in

the frame equals the last octet of the previous frame, the

transmitter replaces the last octet with the control character

/F/ = /K28.7/.

If scrambling is enabled, the following applies:

•

If the last octet of the last frame of the multiframe equals

0x7C, the transmitter replaces the last octet with the control

character /A/ = /K28.3/.

•

On other frames within the multiframe, if the last octet

equals 0xFC, the transmitter replaces the last octet with

the control character /F/ = /K28.7/.

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