AD6677EBZ datasheet(35/48 Pages) AD

35 / 48 page

Data Sheet

AD6677

Rev. C | Page 35 of 48

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the

chip configuration registers (Address 0x00 to Address 0x02);

the ADC functions registers, including setup, control, and test

(Address 0x08 to Address 0xA8); and the transfer register

(Address 0xFF).

The memory map register table (see Table 17) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x14,

the output mode register, has a hexadecimal default value of

0x01. This means that Bit 0 = 1 and the remaining bits are 0s.

This setting is the default output format value, which is twos

complement. For more information on this function and others,

see the Application Note AN-877, Interfacing to High Speed ADCs

via SPI. This application note details the functions controlled by

Address 0x00 to Address 0x21 and Address 0xFF, with the ex-

ception of Address 0x08 and Address 0x14. The remaining

registers, Address 0x08, Address 0x14, and Address 0x3A

through Address 0xA8, are documented in the Memory Map

Open and Reserved Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Unused bits of a

valid address location must be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), do not write to this address

location.

Default Values

After the AD6677 is reset, critical registers are loaded with default

values. The default values for the registers are given in the

memory map register table (see Table 17).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x09, Address 0x0B, Address 0x0D, Address 0x10,

Address 0x14, Address 0x18, Address 0x21, and Address 0x3A

to Address 0x4C are shadowed. Writes to these addresses do not

affect device operation until a transfer command is issued by

writing 0x01 to Address 0xFF, setting the transfer bit. This allows

these registers to be updated internally and simultaneously when

the transfer bit is set. The internal update takes place when the

transfer bit is set, and then the bit autoclears.

AD6677EBZ датащи(PDF) 35 Page - Analog Devices

AD6677EBZ датащи(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL