MFC2000 datasheet(156/426 Pages) ETC

156 / 426 page

MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

7-8

Conexant

100723A

Bits 7-4

StartNeg (0-15)

StartNeg establishes the location of the START signal trailing edge.

Bits 3-0

StartPos (0-15)

StartNeg establishes the location of the START signal leading edge.

Name/Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Start Config

(StartConfig)

$01FF889D

Guardband

Enable for

scctrl[6]

Guardband

Enable for

scctrl[5]

Guardband

Enable for

scctrl[4]

Guardband[4:0]

(in terms of pixel period)

Rst. Value

00h

Read Value

00h

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Start Config

(StartConfig)

$01FF889C

Offset[3:0]

(in terms of pixel period)

Length[3:0]

(in terms of pixel period)

Rst. Value

xxxxxxx0b

Read Value

00h

Bit 15-13 Guardband Enable for scctrl[6:4]

When a guardband is enabled, then the corresponding control signal

will not change (will be “frozen”) for the duration specified by

“guardband” in bit 12-8.

Bit 12-8

Guardband[4:0]

Some scanner requires a quiet period while start pulse is active.

Within this quiet period, only the start pulse will be toggling while other

control signals are prevented from toggling. The duration of this period

is determined by guardband * pixelperiod.

Bit 7-4

Offset[3:0]

The start pulse can be moved with respect to the start of scan cycle by

this offset value which is expressed in terms of pixel period.

Bit 3-0

Length[3:0]

The duration of the start pulse is programmable according to this

“Length” value.

Start pulse duration is [length + 1] * pixel_period

Name/Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Clk2a Edges

(Clk2aEdges)

$01FF889F

(Not Used)

Rst Value

xxh

Read Value

00h

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Clk2a Edges

(Clk2aEdges)

$01FF889E

Clk2aNeg Value (0-15)

Clk2aPos Value (0-15)

Rst Value

00h

Read Value

00h

Bits 7-4

Clk2aNeg

Clk2aNeg establishes the trailing edge of the Clk2a signal relative to

the start of each dot period, and is specified in ScanDotScaler Clock

periods.

Bits 3-0

Clk2aPos

Clk2aPos establishes the leading edge of the Clk2a signal relative to

the start of each dot period, and is specified in ScanDotScaler Clock

periods.

MFC2000 датащи(PDF) 156 Page - List of Unclassifed Manufacturers

MFC2000 датащи(HTML) 156 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL