MFC2000 datasheet(248/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

12-2

Conexant

100723A

Caution: The vertical print motor pattern register (VPMPattern register) can only be written

when it is used as the GPO function. In other words, bit 0 of the GPIOConfig register is set to 1.

Then, CPU sets bit 0 of the GPIOConfig register to 0 and enables the vertical print motor stepping. The content

(the 1st step timer value) of the step timer register is automatically loaded into the step timer and at the same time

an interrupt is generated (the step pulse is blocked at this time). CPU writes the 2nd step timer value into the step

timer register in the stepping interrupt routine. When the step timer expires (timed-out), A pulse is generated to

change the phase pattern to the next one (the 1st step) and the content (the 2nd step timer value) of the step

timer register is automatically loaded into the step timer and an interrupt is generated to inform CPU to load the

3rd step timer value to the step timer register.

At the near end of the motor stepping, a pulse is generated to change the phase pattern to the next one (the ‘n-2’

step, n: the last step) and the content of the step timer register (the time interval between the ‘n-2’ and ‘n-1 steps)

is automatically loaded into the step timer and an interrupt is generated to inform CPU to load the last step timer

value to the step timer register when the step timer expires (timed-out). When the step timer expires again (timed-

out), A pulse is generated to change the phase pattern to the next one (the ‘n-1’ step) and the content (the last

step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated

to inform CPU to load the large dummy timer value to the step timer register. Finally, a pulse is generated to

change the phase pattern to the next one (the last step) and the content (the large dummy timer value) of the step

timer register is automatically loaded into the step timer and an interrupt is generated to inform CPU to disable the

motor stepping. The step timer is cleared to 0 and the stepping pulse is blocked immediately after CPU disables

the motor stepping.

The step enable bit in the VPStepCtrl register only controls if the motor pattern is allowed to change to the next

one. The motor pattern in the VPMPattern register always goes out. CPU has the responsibility to write value

‘00h’ to the VPMPattern register or set bit 4 of the VPStepCtrl register to a proper value according to the external

power control circuit for not driving the vertical print motor. Bit 4 value of the VPStepCtrl register directly goes out

of the MFC2000 chip through the GPIO[13]/SASTXD/PMPWRCTRL pin.

Caution: The GPIO[13]/SASTXD/PMPWRCTRL pin can only be used as the PMPWRCTRL pin

when bit11 of the GPIOConfig1 register is ‘0’ and bit 12 of the GPIOConfig1 register is ‘1’.

The time interval between two adjacent stepping pulses (for example, t1 and t2) is determined by the timer value.

The min. time difference between two adjacent stepping pulses (It is called the timer resolution, for example,

∆ t =

| t2-t1|.) is determined by the frequency of the stepping clock (See Figure 12-2).

time is controlled by

the step timer

STEPPULSE

(in the speed-up period)

Figure 12-2. Stepping Timing

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