MFC2000 datasheet(219/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

9-7

Input data FIFO Control register for the data from the external memory (for DMA channel 9):

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Bi-level Resolution

Conversion Input

Data FIFO Control

(BiRCInFIFOCtrl)

$01FF807B

FIFO

Enabled

(R)

Data

Request

(R)

FIFO

Ready

(R)

FIFO DMA Threshold

FIFO Output Pointer

Rst Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Bi-level Resolution

Conversion Input

Data FIFO Control

(BiRCInFIFOCtrl)

$01FF807A

(Not Used)

Holding

(Not Used)

FIFO Data Quantity

FIFO Input Pointer

Rst Value

x0x00000b

Read Value

00h

Bit 15

This bit indicates that the FIFO is active and capable of generating

DMA requests.

Bit 14

This bit is essentially a copy of the DMA Request output signal and

indicates that the FIFO wishes to transfer data.

Bit 13

This bit indicates that the FIFO can accept data transfers to/from the

local logic. This bit is low when the data direction is into the local logic

and the FIFO is empty or when the data direction is out of the local

logic and the FIFO is full.

Bit 12-10

This bit field indicates at which point the FIFO should issue a

DMA request. It is compared with the FIFO Data Quantity bit field

to determine when this should occur. Legal values are from

0 to 4. Values greater than 4 are treated as 4.

Bit 9-8

This bit field indicates which byte of the FIFO quad halfword structure

is the next to be used as output data.

Bit 6

This bit indicates that there is a full word in the holding register

Bit 4-2

This bit field indicates the number of quad halfwords that contain data.

Valid values are from 0 to 4.

Bit 1-0

This bit field indicates which byte of the FIFO quad halfword structure

is the next to receive input data.

Note: It is strongly recommended that the FIFO be disabled before firmware writes to the FIFO

Control register. The FIFO Control register contains data that is essential to the FIFO’s

operation. If this data is changed while the FIFO is operating, unpredictable operation will result.

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